Table 7-21. Dynmrcon Register; Table 7-22. Dynmrcon Fields; Dynamic Memory Read Configuration Register (Dynmrcon) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON)

This register allows configuration of the dynamic memory Read strategy. This register
should only be modified during initialization. This register provides the Read strategy for
all four dynamic memory Chip Select signals. The DYNMRCON resets to 0x00, which is
invalid. Therefore, this register must be programmed to 0x01 during initialization if the
SDRAM controller is used.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:2
1:0

Table 7-21. DYNMRCON Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-22. DYNMRCON Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Read Data Strategy This field selects the Read strategy.
00 = Reserved
RDS
01 = Command Delayed Strategy (Clock Out not delayed; command delayed)
10 = Reserved
11 = Reserved
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x028
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
RDS
0 0
RW RW
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