Table 7-25. Dynm2Pre Register; Table 7-26. Dynm2Pre Fields; Dynamic Memory Active To Precharge Command Period Register (Dynm2Pre) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
7.5.2.8 Dynamic Memory Active to Precharge Command Period
Register (DYNM2PRE)
The Dynamic Memory Active to Precharge Command Period Register enables program-
ming the Active to Precharge Command Period, tRAS. This value is normally found in
SDRAM data sheets as t
This register should only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering Low-
Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0). When
in these two modes, external memory access is not allowed, ensuring that changing
parameters will not corrupt external data. Low-Power Mode automatically refreshes
SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh (DYNMC-
TRL:SR = 1) prior to entering Disable.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
.
RAS

Table 7-25. DYNM2PRE Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-26. DYNM2PRE Fields

BITS NAME
31:4 /// Reserved Reading returns 0. Write the reset value.
Active to Precharge Command Period
3:0 tRAS
Period = (tRAS + 1) External Memory Clock periods
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x034
FUNCTION
Version 1.0
External Memory Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
tRAS
1 1
RW RW
7-37