Chapter 5 - Direct Memory Access Controller; Table 5-4. Sourcelo Register; Table 5-5. Sourcelo Fields; Table 5-6. Sourcehi Register - Sharp LH79524 User Manual

Direct Memory Access Controller

5.2.2 Register Definitions

5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI)
The two 16-bit Source Base Registers contain the 32-bit source base address for the next
DMA transfer. When the DMA Controller is enabled, the contents of the Source Base Reg-
isters load into the Current Source Address Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0
5-6

Table 5-4. SOURCELO Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 5-5. SOURCELO Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Low Order Source Address This field contains the lower 16-bits
SOURCELO
of the address for the source of data for the next DMA transfer.

Table 5-6. SOURCEHI Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 5-7. SOURCEHI Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
High Order Source Address This field contains the upper 16-bits
SOURCEHI
of the address for the source of data for the next DMA transfer.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
SOURCELO
0 0 0 0
RW RW RW RW
DATASTREAM x BASE + 0x000
DESCRIPTION
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
SOURCEHI
0 0 0 0
RW RW RW RW
DATASTREAM x BASE + 0x004
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW