Table 4-47. Alitiming1 Register; Table 4-48. Alitiming1 Fields; Timing Delay Register 1 (Alitiming1) - Sharp LH79524 User Manual

Color Liquid Crystal Display Controller

4.5.6.3 Timing Delay Register 1 (ALITIMING1)

The ALITIMING1 Register is used for various delays values for output signals. All delays
are specified in number of LCD clock (LCDDCLK) periods.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:14
13:12 MODDEL
11:8
7:4
3:0
4-40

Table 4-47. ALITIMING1 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// MODDEL
0 0 0 1 0
RO RO RW RW RW

Table 4-48. ALITIMING1 Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
LCDMOD LOW Delay Controls the delay (number of LCDSPS rising edges)
to hold LCDMOD LOW before transitioning HIGH.
MODDEL = (LCDSPS rising edges) – 1
LCDPS and LCDCLS Delay Controls the delay in LCDDCLK periods from
the first rising edge of the internal CLCDC clock after the leading edge of the
internal LCDLP signal (not the LCDLP pin no. 137), to the leading edge of the
PSCLS
LCDREV signal. The value of this field must be greater than 0.
PSCLS = (LCDDCLK periods) – 1
Polarity-Reversal Delay* Controls the delay in LCDDCLK periods from the
first assertion of the LCDLP (horizontal sync) signal, to the falling edge of the
REVDEL
LCDREV signal. The value of this field must be greater than 0.
REVDEL = (LCDDCLK periods) – 1
LCDLP Delay Controls the delay in LCDDCLK periods from the first rising
edge of the internal CLCDC clock after the leading edge of the internal LCDLP
signal (not the LCDLP pin no. 137), to the leading edge of the LCDLP signal.
LPDEL
The value of this field must be greater than 0.
LPDEL = (LCDDCLK periods) – 1
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
PSCLS
0 0 0 0
RW RW RW RW
0xFFFE4000 + 0x008
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
REVDEL LPDEL
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 0
RW RW