Table 16-2. Uart Register Summary; Interrupts - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

16.2 Interrupts

UART0, UART1, and UART2 each have a combined interrupt. The individual UART inter-
rupt outputs are ORed together to produce the combined interrupt for that UART. Interrupt
conditions within the combined interrupt are individually maskable. The Vectored Interrupt
Controller (VIC) must be programmed before using the UART interrupts. Refer to
Section 18.1.2 to program the VIC.
16.2.1 UARTINTR
The UARTINTR interrupt is the combined interrupt for each UART. It is asserted if one or
more of the other interrupts are asserted.
16.3 Register Reference
This section provides the UARTs' register memory mapping and bit fields.
16.3.1 Memory Map
The base address for UART0 is 0xFFFC0000; the base address for UART1 is
0xFFFC1000; the base address for UART2 is 0xFFFC2000. Table 16-2 shows the
memory map for the UART registers

Table 16-2. UART Register Summary

ADDRESS
OFFSET
0x000
UARTDR
0x004
UARTRSR/UARTECR
0x008 - 0x014
0x018
UARTFR
0x01C
0x020
UARTILPR
0x024
UARTIBRD
0x028
UARTFBRD
0x02C
UARTLCR_H
0x030
UARTCR
0x034
UARTIFLS
0x038
UARTIMSC
0x03C
UARTRIS
0x040
UARTMIS
0x044
UARTICR
0x048
DMACTRL
0x04C - 0x07C
0x080 - 0x08C
0x090 - 0xFFC
NAME
Data Register
Receive Status Register (Read)
Error Clear Register (Write)
Reserved — Do not access
///
Flag Register
Reserved — Do not access
///
IrDA Low Power Counter Register
Integer Baud Rate Divisor Register
Fractional Baud Rate Divisor Register
Line Control Register, HIGH byte
Control Register
Interrupt FIFO Level Select Register
Interrupt Mask Set/Clear Register
Raw Interrupt Status Register
Masked Interrupt Status Register
Interrupt Clear Register
UART0 DMA Control Register
Reserved — Do not access
///
Reserved — Do not access
///
Reserved — Do not access
///
Version 1.0
DESCRIPTION
UARTs
16-7