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Boot Controller
3.1 Theory of Operation
The Boot Controller is a slave module that connects to the APB. It provides hardware sup-
port for configuring the External Memory Controller (EMC) interface on power-up, and
allows multiple boot devices and scenarios to be used in different applications. The Boot
Controller employs no error checking other than that specified by a protocol, if applicable,
and does not utilize the MMU or caches.
Booting can occur from one of several devices. The Boot Controller reads the status of
Port C and determines the type of device from which the code will be transferred. Once
the device and location is determined, the Boot Controller reads exactly 4KB (small-block
devices, I
it at physical address 0x60000000. Finally, the Boot Controller transfers control to that
code by setting the Program Counter to 0x60000000 and removes the Boot ROM from the
memory map (the Boot ROM is only visible in the memory map immediatly following reset).
When using small-block devices, the Boot Controller transfers 4KB of code from the boot
device. With large-block devices, the Boot Controller transfers 1KB. This is because
large-block devices send an ECC value at the end of each page, which would corrupt
the code stream.
When using either type device, but especially with large-block devices, larger amounts of
boot code can be loaded by writing a bootstrap loader for the initial code, which would then
execute and transfer the balance of the boot code to internal SRAM.
3.1.1 Boot Device Determination
The Boot Controller determines type and location of an external non-volatile device from
which boot code will be loaded for SoC core execution. This location must be within the
nCS1 chip select domain for all devices but NAND Flash.
The booting process is controlled by the initial values of PC[7:4]. The value on these pins at
power-up determines the boot device, data bus width, and configuration of control signals.
The Boot Controller then configures the External Memory Controller for proper accesses.
Table 3-1 lists the configuration ONLY for version A.0 of the SoC. For versions A.1 and
later, refer to Table 3-2.
3-2
2
C, or UART) or 1KB (large-block devices) of code from that location and stores
Version 1.0
LH79524/LH79525 User's Guide
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