Figure 7-1. External Memory Controller Block Diagram - Sharp LH79524 User Manual

External Memory Controller
The EMC supports six banks of external memory. Together these banks occupy 384MB of
address space. For an SRAM memory cycle, bits 31 through 26 are decoded to select the
proper memory clock phase and the proper Chip Select. Bits 25 through 2 are passed as
the external address to the memory bank for 32-bit external memory widths, bits 24
through 1 are passed for 16-bit external memory widths and bits 23 through 0 are passed
for 8-bit external memory widths. Regardless of the memory width, the least significant
address bit appears on pin 'A0'. For example, when interfacing with 32-bit memory, pin A0
carries the A2 address signal and pin A23 carries the A25 address signal. This is a bit dif-
ferent than many memory interfaces, but offers advantages such as a greater addressing
space for 16- and 32- bit memory systems.
During an SDRAM memory cycle, the bank being accessed is selected by the assertion
of the appropriate Chip Select signal. This is found by decoding address bit 28. A value of
0 causes Chip Select 0 to be asserted. Address bits 27 through 0 are passed as the exter-
nal address to the memory bank.
Timing diagrams for both static and dynamic memory transactions are found in the
Data Sheet.
7-2
APB
INTERFACE
ENDIANIZATION
TEST INTERFACE CONTROLLER

Figure 7-1. External Memory Controller Block Diagram

Version 1.0
LH79524/LH79525 User's Guide
MEMORY
CONTROL
DATA
BUFFERS
and
PACKING
LOGIC
SDRAM
LOW-POWER
SDRAM
SYNCHRONOUS
FLASH
SDRAM
ROM
FLASH
LH79525-62