Table 13-26. Ahbclkctrl Register; Table 13-27. Ahbclkctrl Fields; Ahb Clock Control Register (Ahbclkctrl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.11 AHB Clock Control Register (AHBCLKCTRL)

This register controls the AHB clocks to several peripherals. Programming a bit to 1 disables
the AHB clock to the corresponding peripheral. Following reset, all AHB clocks are enabled.
For unused peripherals, software should program a 1 to the corresponding bit in this reg-
ister to reduce overall power consumption.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 13-26. AHBCLKCTRL Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-27. AHBCLKCTRL Fields

BITS NAME
31:5 /// Reserved Reading returns 0. Write the reset value.
AHB LCD Clock
4 LCD
1 = Disables the LCD AHB clock
0 = Enables the LCD AHB peripheral clock
AHB USB Clock
3 USB
1 = Disables the USB AHB clock
0 = Enables the USB AHB peripheral clock
AHB ETHERNET Clock
2 ETHERNET
1 = Disables the ETHERNET AHB clock
0 = Enables the ETHERNET AHB peripheral clock
AHB External SDRAM Controller Clock
1 SDRAM
1 = Disables the SDRAM AHB clock
0 = Enables the SDRAM AHB peripheral clock
AHB DMA Clock
0 DMA
1 = Disables the DMA AHB clock
0 = Enables the DMA AHB peripheral clock
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFE2000 + 0x2C
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
LCD USB
0 0 0 0 0
RO RO RW RW RW
17 16
0 0
RO RO
1 0
DM
A
0 0
RW RW
13-21