Table 13-52. Syspllctl Register; Table 13-53. Syspllctl Fields; System Pll Control Register (Syspllctl) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.22 System PLL Control Register (SYSPLLCTL)

This register controls the System PLL frequency. System PLL frequency is calculated by:
SystemPLLfrequencySystem
The maximum System PLL frequency is 304.819 MHz.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:14
13
12
11:6
5:0
SystemClockOscillatorFrequency
=
---------------------------------------------------------------------------------------------------------------------------------------------------

Table 13-52. SYSPLLCTL Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
/// ///
0 0 1 0 0
RO RO RW RW RW

Table 13-53. SYSPLLCTL Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
/// Reserved Reading returns 0. Write 1 only.
System PLL Output Frequency Range Select
SYSFRANGE
1 = 100 MHz to 304.819 MHz (best jitter performance achieved)
0 = 20 MHz to 100 MHz
System PLL Pre-Divider Prescales the System PLL Reference
SYSPREDIV clock. The divisor chosen must satisfy the equation:
(System Clock Oscillator frequency) ÷ (SYSPREDIV) ≥ 5 MHz
System PLL Loop-Divider Prescales the System PLL Feedback
SYSLOOPDIV
clock. The divisor can be programmed from 1 to 63.
Reset, Clock, and Power Controller
SYSPREDIV
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
SYSPREDIV
0 0 0 0
RW RW RW RW
0xFFFE2000 + 0xC0
DESCRIPTION
Version 1.0
×
SYSLOOPDIV
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
SYSLOOPDIV
1 0 0 0 1
RW RW RW RW RW
17 16
0 0
RO RO
1 0
0 1
RW RW
13-33