Sharp LH79524 User Manual page 145

Direct Memory Access Controller
5.1 Theory Of Operation
The SoC uses a central DMA Controller to service all DMA requirements for DMA-capable
devices. The DMA Controller provides DMA support for the DMA-capable peripherals
listed in Table 5-1. The DMA Controller has an APB slave port for programming its
registers and an AHB port for data transfers. The DMA is controlled by the system clock.
NOTE: The DMA Controller is not used for the display system, Ethernet, or USB. The LCD Controller,
The DMA Controller transfers data between AHB peripherals and memory or between
memory and memory. The DMA Controller supports four data streams: Stream 0,
Stream 1, Stream 2, and Stream 3. These data streams can be used to service:
• Four peripheral data streams (peripheral-to-memory or memory-to-peripheral)
• Three peripheral data streams and one memory-to-memory data stream.
The four data streams use a fixed-priority arbitration scheme and share one common
16-word-deep FIFO for buffering burst data. Each of the four data streams has its own
independent set of DMA Registers and address/transfer count counters. In addition:
• Stream 2 provides a set of external signals for initiating and controlling DMA transfers
between external peripherals and memory. The signals DREQ and DACK are brought
out to external pins that are multiplexed with other functions. Note that any peripheral
using the external DMA feature must be mapped into the nCS3 memory space.
• Stream 3 can conduct memory-to-memory DMA transfers under software control.
The DMA Registers are programmed through an APB Slave interface that has a
32-bit data interface.
A stream can be programmed to transfer from 1 to 65,535 data units. In this context, a data
unit represents a group of bits equal in width to the data width of the source peripheral or
memory. The source and destination data widths can be programmed independently to be
byte, half-word, or word (byte only for DMA to/from UART0). Data is transferred in bursts,
with the burst length programmable to 1, 4, 8, or 16 peripheral data units. The stream has
source and destination address registers that can be independently programmed to remain
fixed or increment after each data access.
The peripheral using the external DMA feature must be connected to nCS3. This is neces-
sary to ensure that nDACK will be asserted.
5-2
Ethernet, and USB have their own DMA port that connects directly to the memory system to
retrieve data.
Version 1.0
LH79524/LH79525 User's Guide