Receive Interrupt - Sharp LH79524 User Manual

2
I S Converter

10.1.7.4 Receive Interrupt

SSPRXINTR is the Receive Interrupt. This interrupt is asserted when there are four or more
valid entries in the receive FIFO. The interrupt is cleared by reading the receive FIFO until
there are three or fewer entries. This interrupt originates in the SSP.
10.1.7.5 Transmit Interrupt
SSPTXINTR is the Transmit Interrupt. This interrupt is asserted when the FIFO is less than
or equal to half full (when there is space for four or more entries). The interrupt is cleared
when there are five or more entries in the transmit FIFO. This interrupt originates in the SSP.
10.1.7.6 Receive Overrun Interrupt
SSPRORINTR is the Receive Overrun Interrupt. This interrupt is asserted when the FIFO is
already full and an additional data frame is received, causing an overrun of the FIFO. Data
is over-written in the Shift Register, but not the FIFO. This interrupt originates in the SSP.
10.1.7.7 Receive Timeout Interrupt
SSPRXTOINTR is the Receive Timeout Interrupt. This interrupt is asserted if the receive
FIFO does not generate a further service request interrupt (SSPRXINTR) within a fixed
number of HCLK periods.
10.1.7.8 I2SINTR
The MMPE, SMPE, TXUE, SSPINTR interrupts are combined into the single output
I2SINTR. This interrupt is an OR function of the individual interrupt sources. This combined
interrupt is the only one going to the Vectored Interrupt Controller (VIC).
The combined I
SSP and I
SSPINTR from the SSP.
10-12
2
S Interrupt is asserted if any of the seven individual interrupts from the
2
S Converter are asserted and enabled. The I
Version 1.0
LH79524/LH79525 User's Guide
2
S Interrupt supersedes the