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LH79524/LH79525 User's Guide
Reset, Clock, and Power Controller
13.1.4.5 Stop2 Mode
Stop2 Mode stops all System Clocks and disables both the PLLs and the System Clock
Oscillator that feeds it. However, the 32.768 kHz internal oscillator remains active. This mode
is entered when software writes 0b100 to the PWRDWNSEL field of the CTRL Register.
When an interrupt is received, the RCPC exits Stop2 Mode and ensures an orderly transition
to Active Mode. An interrupt should be held active until the RCPC exits Stop2 Mode.
13.1.4.6 Power Control in JTAG Mode
When using JTAG, the SoC cannot be placed in a low-power mode. This SoC will go into
the low power mode, but is then immediately awakened by debug interrupts. Therefore,
when in JTAG, the SoC should not be commanded to go into a low power mode.
Version 1.0
13-7
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