Table 13-50. Coreconfig Register; Table 13-51. Coreconfig Fields; Core Clock Configuration Register (Coreconfig) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.21 Core Clock Configuration Register (CORECONFIG)

This register can be programmed to select either the Standard Mode or the FastBus exten-
sion for the ARM720T bus interface. In Standard mode, either a synchronous or asynchro-
nous operation can be selected. When changing from Standard Mode to FastBus, the CPU
clock must always be greater than or equal to the system bus clock.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:2
1:0
13-32

Table 13-50. CORECONFIG Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 13-51. CORECONFIG Fields

NAME
/// Reserved Reading is indeterminate. Write the reset value.
Core Clock Configuration Program this field to configure the ARM720T
core clock.
00 = Standard Mode, asynchronous operation
CCLK
01 = FastBus extension mode
10 = Standard Mode, synchronous operation
11 = FastBus extension mode
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO WO
0xFFFE2000 + 0x88
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
WO WO WO WO WO
17 16
0 0
RO RO
1 0
CCLK
0 0
WO WO