Stn Horizontal Timing - Sharp LH79524 User Manual

Color Liquid Crystal Display Controller
4.6 Timing Waveforms
This section describes typical output waveform diagrams for the CLCDC and the ALI.

4.6.1 STN Horizontal Timing

Figure 4-6 shows typical horizontal timing waveforms for STN panels. In this figure, the
CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce
the LCDDCLK output. Programmable registers in the CLCDC set the timings (in terms of
LCDDCLK pulses) to produce the other signals that control an STN display.
For example, Figure 4-6 shows that the duration of the LCDLP signal is controlled by
TIMING0:HSW. Figure 4-6 also shows that the polarity of the LCDLP signal is set by
TIMING2:IHS.
4.6.2 STN Vertical Timing
Figure 4-7 shows typical vertical timing waveforms for STN panels.
4.6.3 TFT Horizontal Timing
Figure 4-8 shows typical horizontal timing waveforms for TFT panels.
4.6.4 TFT Vertical Timing
Figure 4-9 shows typical vertical timing waveforms for TFT panels.
4.6.5 AD-TFT/HR-TFT Horizontal Timing Waveforms
Figure 4-10 shows typical horizontal timing waveforms for AD-TFT and HR-TFT panels.
The ALI adjusts the normal TFT timing to accommodate these panels.
4.6.6 AD-TFT/HR-TFT Vertical Timing Waveforms
Figure 4-11 shows typical vertical timing waveforms for AD-TFT and HR-TFT panels. The
power sequencing and register information is the same as for TFT vertical timing.
4-42 Version 1.0
LH79524/LH79525 User's Guide