Sharp LH79524 User Manual page 514

Universal Serial Bus Device
BITS
3
2
1
0
17-24
Table 17-31. INCSR1 Fields (Cont'd)
NAME
FIFO Flush Request Software programs this bit to 1 if it intends to flush
the IN FIFO. This bit is programmed to 0 by the USB after the FIFO is
flushed (IN_PKT_RDY must be read as a 1 before the USB can program
this bit to 0). The CPU is interrupted when this happens. If a token is in
progress, the USB waits until the transmission is complete before the
FIFO_FLUSH
FIFO is flushed. If two packets are loaded into the FIFO, only the topmost
packet (one that was intended to be sent by the Host) is flushed, and the
corresponding IN_PKT_RDY bit for that packet is cleared.
1 = FIFO flush requested
0 = FIFO flush completed
Underruns In Isochronous mode, this bit is set (1) when a zero length
data packet is sent after receiving an IN token with the IN_PKT_RDY bit
UNDERRUN
not set. In Bulk/Interrupt mode, this bit is set (1) when a NAK is returned
in response to an IN token.
FIFO Not Empty This bit indicates there is at least one data packet in
the FIFO.
1 = Either 2 packets are in the IN FIFO and MAXP is equal to, or less than
FIFO_NE
half of the IN FIFO size; or 1 packet is in the IN FIFO and MAXP is
less than or equal to the IN FIFO size
0 = 1 packet in the IN FIFO
IN Packet Ready After writing a packet of data into the FIFO, software
must program this bit to 1. The USB programs this bit to 0 once the packet
has been successfully sent to the Host. An interrupt is generated when
the USB clears this bit informing the core that the next packet can be load-
ed. While this bit is 1, software cannot write to the FIFO. If the
IN_PKT_RDY
SEND_STALL bit is programmed by software to a 1, this bit cannot be
programmed to 1.
1 = IN FIFO has unsent data
0 = FIFO available for next IN packet
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide