Table 17-8. Iir Register; Table 17-9. Iir Fields; Interrupt Register For Endpoint 0, 1, 2, And 3 (Iir) - Sharp LH79524 User Manual

Universal Serial Bus Device

17.2.2.3 Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR)

IIR is a read-only register that indicates which of the interrupts for IN Endpoints 1, 2, and
3 are currently active. It also indicates whether the Endpoint 0 (the Control Endpoint) inter-
rupt is currently active. Upon interrupt, software should read each of the three interrupt reg-
isters (IIR, OIR, and UIR), which clears the interrupt bit. The UIR must be the last register
read and cleared.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
TYPE
ADDR
BITS NAME
31:4
3 EP3IN
2 EP2IN
1 EP1IN
0 EP0IN
17-12
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
/// Reserved Reading returns 0. Write the reset value.
Endpoint3 IN Interrupt The EP3 interrupt is generated for Interrupt IN transfers. This bit
is programmed to 1 by the USB when: IN_PKT_RDY is cleared to 0 by the USB; The FIFO
is flushed by the USB; and USB has issued a STALL response IN token, indicated by
SENT_STALL = 1. Software clears this interrupt by reading this register.
1 = Interrupt IN transfer pending
0 = Interrupt cleared or the above conditions are not met
Endpoint2 IN Interrupt The EP2 interrupt is generated for Isochronous Interrupt IN transfers.
The USB block programs this bit to 1 when IN_PKT_RDY bit is cleared to 0 by the USB Host,
the FIFO is flushed by the USB Host, and the USB Host has issued a STALL response IN token,
as indicated by SENT_STALL = 1. Software clears this interrupt by reading this register.
1 = Isochronous Interrupt IN transfer pending
0 = Interrupt cleared or the above conditions are not met
Endpoint1 IN Interrupt The EP1 interrupt is generated for BULK IN transfers. The USB
block programs this bit to 1 when IN_PKT_RDY bit is cleared to 0 by the USB Host, the FIFO
is flushed by the USB Host, and the USB Host has issued a STALL response IN token, as
indicated by SENT_STALL = 1. Software clears this interrupt by reading this register.
1 = BULK IN transfer pending and the above three conditions are met
0 = Interrupt cleared or the above conditions are not met
Endpoint 0 Interrupt The EP0 interrupt is generated for Control transfers. The EP0 inter-
rupt is programmed to 1 by the USB block when: OUT_PKT_RDY is set to 1 by the USB Host;
IN_PKT_RDY is cleared to 0 by the USB Host; SENT_STALL is set to 1 by the USB Host;
SETUP_END is set to 1 by the USB Host; and DATA_END is cleared to 0 by the USB Host
(Indicates end of control transfer). Software clears this interrupt by reading this register.
1 = EP0 interrupt set
0 = EP0 interrupt cleared or the above conditions are not met

Table 17-8. IIR Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF5000 + 0x008

Table 17-9. IIR Fields

FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO