Table 14-17. Mis Register; Table 14-18. Mis Fields; Masked Interrupt Status Register (Mis) - Sharp LH79524 User Manual

Synchronous Serial Port

14.2.2.8 Masked Interrupt Status Register (MIS)

MIS is the Masked Interrupt Status Register. When read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:4
3
2
1
0
14-18
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Transmit FIFO Masked Interrupt Status Gives the Transmit FIFO masked
interrupt state.
TXMIS
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
Receive FIFO Masked Interrupt Status Gives the Receive FIFO masked
interrupt state.
RXMIS
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
Receive Timeout Masked Interrupt Status Gives the Receive Timeout
masked interrupt state.
RTMIS
1 = Interrupt asserted
0 = Interrupt not asserted or is masked
Receive Overrun Masked Interrupt Status Gives the Receive Overrun
masked interrupt state.
RORMIS
1 = Interrupt asserted
0 = Interrupt not asserted or is masked

Table 14-17. MIS Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC6000 + 0x01C

Table 14-18. MIS Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO