Table 14-15. Ris Register; Table 14-16. Ris Fields; Raw Interrupt Status Register (Ris) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

14.2.2.7 Raw Interrupt Status Register (RIS)

This register provides the current raw status value of the corresponding interrupt prior to
masking. A write has no effect.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:4
3
2
1
0
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Transmit FIFO Raw Interrupt Status Gives the raw interrupt state (pri-
or to masking) of the Transmit FIFO interrupt.
TXRIS
1 = Interrupt asserted
0 = Interrupt not asserted
Receive FIFO Raw Interrupt Status Gives the raw interrupt state (pri-
or to masking) of the Receive FIFO interrupt.
RXRIS
1 = Interrupt asserted
0 = Interrupt not asserted
Receive Timeout Raw Interrupt Status Gives the raw interrupt state
(prior to masking) of the Receive Timeout interrupt.
RTRIS
1 = Interrupt asserted
0 = Interrupt not asserted
Receive Overrun Raw Interrupt Status Gives the raw interrupt state
(prior to masking) of the Receive Overrun interrupt.
RORRIS
1 = Interrupt asserted
0 = Interrupt not asserted

Table 14-15. RIS Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC6000 + 0x018

Table 14-16. RIS Fields

DESCRIPTION
Version 1.0
Synchronous Serial Port
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO
14-17