Figure 16-1. Uart0, Uart1, And Uart2 Block Diagram; Theory Of Operation - Sharp LH79524 User Manual

UARTs
nUARTRST
SYSTEM CLOCK
PRESETn
PSEL
PENABLE
PWRITE
PADDR[11:2]
PWDATA[15:0]
PRDATA[15:0]
UARTCLK
UARTRXDMACLR
UARTTXDMACLR
UARTRXDMABREQ
UARTTXDMABREQ
nUARTCTS

16.1 Theory of Operation

The three UARTs, UART0, UART1, and UART2, offer similar functionality to the industry-
standard 16C550. They perform serial-to-parallel conversion on data received from a
peripheral device and parallel-to-serial conversion on data transmitted to the UART.
The CPU reads and writes data and control/status information through the AMBA APB
interface. The transmit and receive paths are buffered with internal FIFO memories that
support programmable 'watermark levels', and overrun protection. These FIFO memories
enable up to 32 entries to be stored independently in both transmit and receive
modes. All UART Control and Status Registers can be accessed through the APB.
16-2
READ
DATA[11:0]
WRITE
32 × 9
DATA
TRANSMIT
FIFO
CONTROL AND STATUS
BAUD RATE
APB
DIVISOR
INTERFACE
AND
REGISTER
BLOCK
BAUD
RATE
GENERATOR
REFERENCE CLOCK
FIFO
FLAGS
DMA
INTERFACE

Figure 16-1. UART0, UART1, and UART2 Block Diagram

Version 1.0
LH79524/LH79525 User's Guide
TxD
RxD
BAUD16
TRANSMIT RECEIVE
FIFO FIFO
STATUS STATUS
INTERRUPT
GENERATION
32 × 12
RECEIVE
FIFO
UARTTXD
TRANSMITTER
UARTIRTX
UARTRXD
RECEIVER
UARTIRRX
UARTINTR
nUARTRTS
LH79525-63