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Synchronous Serial Port
14.1.6.2 Transmit Interrupt
SSPTXINTR is the Transmit Interrupt. This interrupt is asserted when the FIFO is less than
or equal to half full (when there is space for four or more entries). The interrupt is cleared
when there are five or more entries in the transmit FIFO.
This interrupt is not qualified with the Synchronous Serial Port Enable bit (bit [4]) in CTRL1,
allowing operation in one of two ways. Data can be written to the transmit FIFO prior to
enabling the SSP and the interrupts. Alternatively, the SSP and interrupts can be enabled
so that data can be written to the transmit FIFO by an ISR. For more information about
Control Register 1, see Section 14.2.2.2. The SSPTXINTR interrupt is always set if the
Synchronous Serial Port Enable bit in Control Register 1 is not set (see Section 14.2.2.2).
14.1.6.3 Receive Overrun Interrupt
SSPRORINTR is the Receive Overrun Interrupt. This interrupt is asserted when the FIFO
is already full and an additional data frame is received, causing an overrun of the FIFO.
Data is over-written in the Shift Register, but not the FIFO.
14.1.6.4 Receive Timeout Interrupt
SSPRXTOINTR is the Receive Timeout Interrupt. This interrupt is asserted when the
receive FIFO is not empty and the SSP has remained idle for a fixed 32 bit-clock period (it
is not programmable). This interrupt ensures that software knows that data remains in the
FIFO and must be read. The interrupt resets if the FIFO is emptied by subsequent Reads
or if new data is introduced to the FIFO. In both master and slave modes, the receive tim-
eout interrupt can be reset by writing to the ICR:RTIC bit, reading the contents of the
receive FIFO until empty, or if new activity occurs on the respective clock lines.
14.1.6.5 SSPINTR
The SSPRXINTR, SSPTXINTR, SSPRORINTR, and SSPRXTOINTR interrupts are also
combined into the single output SSPINTR. This interrupt is an OR function of the individual
interrupt sources. This combined interrupt is the only one going to the vectored interrupt
controller (VIC).
The combined SSP Interrupt is asserted if any of the four individual interrupts is asserted
and enabled.
14-8
Version 1.0
LH79524/LH79525 User's Guide
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