Table of Contents
Advertisement
UARTs
16.1.3 Nine-bit Mode
In Nine-bit Mode, the parity bit of the character frame is used to identify the message as
containing an address or data (parity is not calculated).
Enable Nine-bit Mode by setting bit 9 (9BIT) of UARTLCR_H. Then set or clear bit 8
(ADDTX) to tag the next character written to UARTDR as address (ADDTX=1) or data
(ADDTX=0). After a write to UARTDR, ADDTX automatically resets to 0 so that subse-
quent writes to UARTDR will tag the character as data.
When a character is written to the transmit FIFO, the value of ADDTX at the time the
UARTDR was written is also stored with the character. This tags each character in the
FIFO as either data or address.
When characters are transmitted out of the transmit FIFO in Nine-bit Mode, the value of
ADDTX for each character is substituted for the parity bit in the outgoing frame.
During Nine-bit Mode reception, the Parity Error/Address Received bits in UARTDR,
UARTRSR and UARTRIS are set if an address was received (the parity bit of the incoming
frame is set). They are cleared if data was received (the parity bit of the incoming frame is
clear). As with other error status bits, the UARTDR must be read before status is read.
16.1.4 Status Conditions
The UARTs adhere to these status conditions:
• If a UART fails to detect a 1 for all programmed Stop-bit periods following a data frame,
the UART sets the framing-error status for that frame.
• When Nine-bit Mode is disabled, enabling parity-error detection causes the UART
to compare the parity/address received bit in each frame with the parity required for
the hardware. The UART sets the parity-error/address received status for each frame
containing a parity error.
• When Nine-bit Mode is enabled, parity-error detection is disabled. The UART sets the
parity-error/address received status for each incoming frame containing an address.
• A line break is 0 for all bits (Start bit, data bits, parity bit, and Stop bits). The UART sets
the line-break status for each frame containing a line break.
• The Overrun Error bit (UARTRSR:OE) indicates some frames might have been lost
immediately preceding the frame with the overrun status.
The overrun status is announced by both the Overrun Error bit (UARTRSR:OE) and an
overrun-status bit in a frame in the receiver FIFO. If the receiver FIFO is full and another
frame is received, the receiver enters the overrun state and the UART sets the overrun-
error bit in the UARTRSR. The Overrun Error bit remains set until software writes a 1 to
UARTRCR:OE.
While the receive FIFO remains full, additional data frames at the receive unit are lost and
are not stored in the receive FIFO. When the UART can resume storing frames in the
receiver FIFO, the receiver exits the overrun state. The overrun-status bit in the receive
FIFO is set in the first frame stored after the overrun.
16-4
Version 1.0
LH79524/LH79525 User's Guide
Advertisement
Table of Contents
