Figure 7-12. Static Write Transaction With Zero Wait States - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
The total Read cycle time is the time that the address is valid (in the figures, until the end
of the 'C' time). In general, Read wait states can be derived from the following equation:
tRC (Read cycle time) = tD1 + tD2 + ... tDn + tE0 + tE1 + ... tEn + C, where the length of
each term is one HCLK period, and 'n' is the value programmed in the respective register.
The minimum value for the equation is tRC = tE0 + C, and is thus zero wait state timing.
Thus, Read wait states can be programmed using the appropriate mix of nOE extension
(programmed in SWAITRDx) with nOE assertion delay (programmed in SWAITOENx).
7.2.4.1.2 Write Cycle Wait States
Write timing starts with assertion of the appropriate memory bank chip selects nCSx and
address signals A[23:0]. The write access time is determined by the number of wait states
programmed in the SWAITWRx register. Figure 7-12 shows the minimum write cycle time
with both SWAITWRx ('A') and SWAITWENx ('B') programmed to zero.
NOTES:
With Register Programming:
SWAITWENx = A = 0x0
SWAITWRx = B = 0x0
C = Address hold
HCLK
A[23:0]
D[31:0]
nCSx
nWE or nBLEx

Figure 7-12. Static Write Transaction with Zero Wait States

Version 1.0
VALID ADDRESS
VALID DATA
C
B0
DATA
LATCHED
A0
External Memory Controller
LH79525-111
7-13