System Pll And Usb Pll Reset - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
These modes reduce power consumption as needed, with each mode providing greater
power savings. Active Mode is the normal operating mode. The other modes are entered
via software control. The RCPC returns to Active Mode upon receiving an interrupt.
Seven external interrupt sources pass through the RCPC before being sent to the VIC. The
interrupts entering the RCPC can be individually programmed to be either level-sensitive
or edge-triggered, and either active-HIGH or active-LOW. All interrupts exiting the RCPC
are converted to a format compatible with the VIC.

13.1.1 System PLL and USB PLL Reset

The System PLL and the USB PLL are reset only by a valid reset signal on nRESETIN.
The Watchdog Timer and Software Reset do not reset the PLLs.
13.1.2 Reset Generation
The RCPC generates System Reset output. The nRESETOUT output pin is driven by the
System Reset. The System Reset is asserted by any of these events:
• An external reset (a logic LOW signal on the external nRESETIN input pin)
• A signal from the internal Watchdog Timer (WDT)
• A Soft Reset
The reset latency depends on the System PLL lock state. If the System PLL is locked when
an external reset is asserted, the System Reset output holds eight System Clock (HCLK)
cycles after the external reset is released. Since the WDT and Soft Reset can be generated
only if the System Clock is running, the System PLL must be locked. If the System PLL is not
locked when an external reset is deasserted, the RCPC waits until the System PLL acquires
lock and holds eight System Clock cycles before releasing the system reset output.
13.1.3 Clock Generation
The RCPC generates the System Clock, CPU clock, and on-chip peripheral clocks from:
• The System Clock crystal (connected to the XTALIN input pin and XTALOUT output pin)
• The 32.768 kHz crystal (connected to the XTAL32IN input pin and XTAL32OUT output pin)
• The internally generated PLL clocks.
There are two on-chip programmable PLLs, one for the System Clock and the other
for the USB clock generation. The System PLL frequency can range from 10 MHz to
304.819 MHz by programming the SYSPLLCNTL Register. The USB PLL frequency can
range from 20 MHz to 304.819 MHz by programming the USBPLLCTL Register. The Sys-
tem Clock and CPU clock are derived from the System PLL clock according to the value
programmed in the SYSCLKPRE Register and CPUCLKPRE Register.
13.1.3.1 Enabling Clocks Prior to Programming Registers
The System Clocks connected to the DMA Controller, Ethernet Controller, External
SDRAM Controller, USB Device, and LCD Controller are not active after reset. To activate
these Clocks, program the PCLKCTRL 1 Register. Note that each of these clocks must be
enabled before programming any registers in the particular block.
Reset, Clock, and Power Controller
Version 1.0 13-3