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Chapter 19
Watchdog Timer
19.1 Theory of Operation
The Watchdog Timer (WDT) can be used to ensure that the system does not hang in an
invalid state. In a normally operating system, the WDT is reset periodically by software. If
an event causes software to fail to reset the WDT during a programmed interval, the WDT
can cause an interrupt or a system reset. This reset does not reset the System PLL nor
the USB PLL. The WDT is programmed with a 32-bit timing value in the Control register
(CTL:TOP) and decrements that value on each HCLK cycle. Upon underflow, (timing out)
the WDT causes either:
• A flag to be set in the Reset, Clock, and Power Controller (RESETSTATUS:WDTO),
triggering a system reset, or
• An interrupt is sent to the Vectored Interrupt Controller (VIC).
Note that the interrupt is only recognized in the Active Mode.
Three conditions cause the TOP value to be loaded into the counter:
• After a system reset
• After a counter reset (programming 0x1984 into the RST register)
• After the counter counts down to 0.
When first enabled or when reset, the WDT begins counting from the programmed timing
value. The WDT is enabled by programming the CTL:EN bit to 1. The WDT block diagram
is shown in Figure 19-1. All descriptions apply to both the LH79524 and LH79525.
Version 1.0
19-1
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