Table 6-26. Mask Register; Table 6-27. Mask Fields; Interrupt Mask Register (Mask) - Sharp LH79524 User Manual

Ethernet MAC Controller

6.3.2.11 Interrupt Mask Register (MASK)

The MASK register is a read-only register that shows the status of the interrupt based on
what has been written to the ENABLE and DISABLE registers. As all interrupts are dis-
abled following reset, the interrupt bits in this register are reset to 1.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:14
13
12
11
10
9:8
6-34
31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 1 1
RO RO RO RO RO
NAME
///
PAUSETMZEROMSK
PAUSEFRRXMSK
NOTOKMSK
RECOVERRUNMSK
///
7 TXCOMPMSK
6 TXBUFEXHMSK
5 RETRYLMTEXMSK
4 TXBUFUNDERMSK
3 TXUSEDBITMSK
2 RXUSEDBITMSK
1 RXCOMPMSK
0 MNGDONEMSK

Table 6-26. MASK Register

26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
///
1 1 1 1 1
RO RO RO RO
0xFFFC7000 + 0x30

Table 6-27. MASK Fields

Reserved Reading returns 0. Write the reset value.
1 = Pause Time Zero Interrupt masked
0 = Unmasked
1 = Pause Frame Received Interrupt masked
0 = Unmasked
1 = Response 'Not OK' Interrupt masked
0 = Unmasked
1 = Receive Overrun Interrupt masked
0 = Unmasked
Reserved Reading returns 0. Write the reset value.
1 = Transmit Complete Interrupt masked
0 = Unmasked
1 = Transmit Buffers Exhausted In Mid-frame Interrupt masked
0 = Unmasked
1 = Retry Limit Exceeded interrupt masked
0 = Unmasked
1 = Transmit Buffer Underrun interrupt masked
0 = Unmasked
1 = Transmit Used Bit Read interrupt masked
0 = Unmasked
1 = Receive Used Bit Read interrupt masked
0 = Unmasked
1 = Receive Complete interrupt masked
0 = Unmasked
1 = Management Done interrupt masked
0 = Unmasked
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19
0 0 0 0
RO RO RO RO
6 5 4 3
1 1 1 1
RO RO RO RO
FUNCTION
18 17 16
0 0 0
RO RO RO
2 1 0
1 1 1
RO RO RO