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Chapter 10
2
I
S Converter
The Synchronous Serial Port (SSP) to I
chronous serial communication stream in TI DSP-compatible mode into an I
synchronous serial stream. The I
slave mode.
• The I
– Programmable Word Select (WS) delay
– Left/right channel information:
– Current WS value at the pin
– WS value associated with next entry written to TX FIFO
– WS value associated with next entry read from RX FIFO
– Ability to invert WS state
– Ability to invert the bit clock
• Supports frame size of 16 bits only. Any other frame size will result in a frame size error.
Each frame transmits starting with the most-significant bit.
• Master and Slave modes supported
• A single combined interrupt is generated as an OR function of the individual interrupt
requests.
• Additional interrupts:
– Transmit FIFO underrun
– SSP Protocol error
– External CODEC Protocol error
• Passes SSP data unaltered when module is not enabled.
• Loopback Test Mode support.
Figure 10-1 shows a block diagram of the I
2
S converter provides:
2
S converter is an interface that converts a syn-
2
S converter operates on serial data in both master and
2
S Converter.
Version 1.0
2
S compliant
10-1
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