Table 4-13. Clcdc Register Summary; Clcdc Register Reference - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

4.5 CLCDC Register Reference

This section contains the register definitions for the CLCDC. ALI registers are found in the
next section.
4.5.1 Enabling the CLCDC
Following reset, the CLCDC Data Clock is gated OFF. Prior to using the CLCDC, it
must be enabled by turning on the LCD Data Clock in the PCLKCTRL1 register of the
Reset, Clock, and Power Controller block (see Section 13.2.2.10). Registers cannot
be programmed until the LCD Data Clock is enabled.
4.5.2 CLCDC Memory Map
The base address for the CLCDC is: 0xFFFF4000
ADDRESS
OFFSET
0x034 - 0x1FC
0x200 - 0x3FC
0x400 - 0x7FF

Table 4-13. CLCDC Register Summary

NAME
TIMING0
0x000
0x004 TIMING1
0x008 TIMING2
0x00C ///
0x010 UPBASE
0x014 LPBASE
0x018 INTREN
0x01C CTRL
0x020 STATUS
0x024 INTERRUPT Masked Interrupt Status Register
0x028 INTCLR
0x02C UPCURR
0x030 LPCURR
///
PALETTE
///
Color Liquid Crystal Display Controller
DESCRIPTION
Horizontal Axis Timing Control
Vertical Axis Timing Control
Clock and Signal Polarity Control Register
Reserved — Do not access
Upper Panel Frame Buffer Base Address Register
Lower Panel Frame Buffer Base Address Register
Interrupt Enable Register
Panel Parameters, Panel Power, and Control
Raw Interrupt Status Register
Interrupt Clear Register
Upper Panel Frame Buffer Current Address Register
Lower Panel Frame Buffer Current Address Register
Reserved — Do not access
256 × 16-bit Color Palette Register. Palette is addressed at 32 bits.
Reserved — Do not access
Version 1.0 4-19