Sharp LH79525 Manuals

Table of Contents

• • 3

    Table of Contents
  • 36

    Preface
    • 36

      Conventions and Terms
      • 36

        Unconnected (Floating) Inputs
      • 36

        Multiplexed Pins
      • 37

        Pin Names
      • 37

        Peripheral Devices
      • 37

        Register Addresses
      • 38

        Register Tables
      • 38

        Table 1. Register Name
      • 38

        Table 2. Bit Fields
      • 39

        Numeric Values
      • 39

        Block Diagrams
      • 39

        Figure 1. Multiplexer
      • 40

        Figure 2. Register with Bit-Field Named
      • 40

        Figure 3. Register with Multiple Bit-Fields Named
      • 40

        Figure 4. Register with Bit-Field Numbered
    • 41

      What's in This User's Guide

• 41

  Chapter 1 - Overview

• 41

  Chapter 2 - ADC and Brownout Detector

• 41

  Chapter 3 - Boot Controller

• 41

  Chapter 4 - Color LCD Controller

• 41

  Chapter 5 - DMA Controller

• 42

  Chapter 11 - I/O Configuration

• 42

  Chapter 12 - Real Time Clock

• 42

  Chapter 13 - Reset, Clock Generation and Power Control

• 42

  Chapter 14 - Synchronous Serial Port

• 42

  Chapter 7 - External Memory Controller

• 42

  Chapter 8 - General Purpose Input/Output

• 43

  Appendix - Glossary

• 43

  Chapter 15 - Timers

• 43

  Chapter 16 - Uarts

• 43

  Chapter 17 - USB Device

• 43

  Chapter 18 - Vectored Interrupt Controller

• 43

  Chapter 19 - Watchdog Timer

• 44

  Chapter 1 - Overview

  • 44

    Table 1-1. LH79524/LH79525 Differences
    • 45

      Figure 1-1. LH79524/LH79525 Block Diagram
    • 46

      1.1 Bus Architecture
    • 46

      1.2 Power Supply
      • 46

        1.2.1 Linear Regulator
    • 47

      1.3 Clock Strategy
      • 47

        Table 1-2. Clock Descriptions
      • 49

        1.3.1 Bus Clocking Modes
        • 49

          1.3.1.1 Standard Bus Clocking Modes
        • 49

          Figure 1-2. Standard Clocking Modes
        • 50

          1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes
        • 50

          1.3.1.3 Fastbus Extension Bus Clocking Mode
        • 50

          Figure 1-3. Fastbus Clocking Mode
    • 51

      1.4 Reset Strategy
      • 51

        Table 1-3. Port C Settings for Boot
      • 52

        1.4.1 Resetting the Test Access Port Controller
      • 52

        Figure 1-4. Reset Circuit for TAP Controller
      • 53

        Figure 1-5. Reset Circuit for TAP Controller Including a Push Button
      • 53

        Hardware Requirements at Reset
        • 54

          Active Pull Ups
        • 54

          Figure 1-6. Active Pullup Circuit
        • 55

          Table 1-4. Default Bus Master Priority
    • 55

      AHB Bus Master Priority and Arbitration

• 56

  Chapter 1 - Overview

  • 56

    Table 1-5. AHB Memory Mapping
    • 56

      Table 1-6. External Static Memory Section Mapping
    • 57

      Table 1-7. SDRAM Memory Section Mapping
    • 57

      Table 1-8. Internal SRAM Memory Section Mapping
    • 57

      Table 1-9. Boot ROM Memory Section Mapping
    • 58

      Table 1-10. AHB Memory Map On Power-Up When Boot Configuration = 0Bx1Xx
    • 58

      Table 1-11. Primary AHB Peripheral Register Mapping
    • 59

      Table 1-12. APB Peripheral Register Mapping
    • 60

      Instruction and Data Cache
    • 61

      Theory of Operation
      • 62

        Figure 2-1. ADC Block Diagram
      • 63

        Bias-And-Control Network
      • 64

        Figure 2-2. Bias-And-Control Network Block Diagram
      • 65

        Clock Generator
      • 65

        Figure 2-3. Simplified N-Bit SAR Architecture
      • 66

        Figure 2-4. Example of a 4-Bit SAR ADC Operation
      • 67

        Battery Control Feature
      • 67

        Figure 2-5. Use of the BATCNTL Pin
      • 68

        Timing Formulas
        • 69

          Pen Interrupt
        • 70

          Table 2-1. ADC Register Summary
        • 70

          Register Reference
        • 71

          Table 2-2. HW Register
        • 71

          Table 2-3. HW Fields
        • 71

          Register Descriptions

• 72

  Chapter 2 - Analog-To-Digital Converter/Brownout Detector

  • 72

    Table 2-4. in + Mux Definition
    • 73

      Low Word Register (LW)
    • 73

      Table 2-5. LW Register
    • 73

      Table 2-6. LW Fields
    • 74

      Results Register (RR)
    • 74

      Table 2-7. RR Register
    • 74

      Table 2-8. RR Fields
    • 75

      Interrupt Mask Register (IM)
    • 75

      Table 2-10. IM Fields
    • 75

      Table 2-9. IM Register

• 76

  Chapter 2 - Analog-To-Digital Converter/Brownout Detector

  • 76

    Table 2-11. PC Register
    • 76

      Power Configuration Register (PC)
    • 76

      Table 2-12. PC Fields
    • 77

      Table 2-13. Touch Screen Controller Power Modes
    • 78

      General Configuration Register (GC)
    • 78

      Table 2-14. GC Register
    • 78

      Table 2-15. GC Fields
    • 79

      General Status Register (GS)
    • 79

      Table 2-16. GS Register
    • 79

      Table 2-17. GS Fields
    • 80

      Interrupt Status Register (IS)
    • 80

      Table 2-18. IS Register
    • 80

      Table 2-19. IS Fields
    • 81

      FIFO Status Register (FS)
    • 81

      Table 2-20. FS Register
    • 81

      Table 2-21. FS Fields
    • 82

      Control Bank Registers
    • 82

      Table 2-22. Sample Entries for Control Bank
    • 83

      Idle High Word Register (IHWCTRL)
    • 83

      Table 2-23. IHWCTRL Register
    • 83

      Table 2-24. IHWCTRL Fields
    • 84

      Idle Low Word Register (ILWCTRL)
    • 84

      Table 2-25. ILWCTRL Register
    • 84

      Table 2-26. ILWCTRL Fields
    • 85

      Masked Interrupt Status Register (MIS)
    • 85

      Table 2-27. MIS Register
    • 85

      Table 2-28. MIS Fields
    • 86

      Interrupt Clear Register (IC)
    • 86

      Table 2-29. IC Register
    • 86

      Table 2-30. IC Fields
    • 87

      Figure 3-1. Boot Controller Block Diagram

• 88

  Chapter 3 - Boot Controller

  • 88

    Theory of Operation
    • 89

      Table 3-1. Boot Configuration for Silicon Version A.0
    • 90

      NAND Flash Operation
    • 91

      Figure 3-2. Active Pullup Circuit
    • 91

      NAND Flash Hardware Design
      • 91

        Table 3-3. Alternate Pin Function During NAND Flash Booting
      • 92

        Table 3-5. Supported Devices
      • 93

        Booting From UART
      • 93

        Table 3-6. UART0 Boot Parameters
      • 93

        Table 3-7. Boot Controller Register Summary
      • 94

        Register Definitions
      • 94

        Table 3-8. PBC Register
      • 94

        Table 3-9. PBC Fields
      • 95

        Ncs1 Override Register (CS1OV)
      • 95

        Table 3-10. CS1OV Register
      • 95

        Table 3-11. CS1OV Fields
      • 96

        External Peripheral Mapping Register (EPM)
      • 96

        Table 3-12. EPM Register
      • 96

        Table 3-13. EPM Fields
      • 97

        Figure 4-1. LH79524/LH79525 LCD System, Simplified Block Diagram

• 97

  Chapter 4 - Color Liquid Crystal Display Controller

  • 97

    Introduction
    • 98

      Figure 4-2. Block Diagram of a Typical Advanced LCD Panel
    • 98

      LCD Panel Architecture
  • 99

    CLCDC Features
    • 100

      Figure 4-3. Color LCD Controller Block Diagram
    • 101

      Supported Displays and Panels
    • 102

      Pixel Serializer
    • 102

      Table 4-1. Pixel Display Arrangement
    • 102

      Table 4-2. Frame Buffer Pixel Storage Format [31:16]
    • 103

      Table 4-3. Frame Buffer Pixel Storage Format [15:0]
    • 104

      Palette RAM
      • 105

        Grayscale Algorithm
      • 106

        Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels
      • 106

        Table 4-7. Supported Color STN LCD Panels (LH79524 Only)
      • 106

        Table 4-8. Supported Mono-Stn LCD Panels
    • 104

      Table 4-4. Palette Data Storage (LH79525 with 12-Bit CLCDC)
    • 104

      Table 4-5. Palette Data Storage (LH79524 with 16-Bit CLCDC)

• 107

  Chapter 4 - Color Liquid Crystal Display Controller

  • 107

    Table 4-9. Color STN Intensities From Gray-Scale Modulation
    • 108

      Table 4-10. LH79524 LCD Data Multiplexing
    • 109

      LCD Interface Timing Signals
      • 110

        LCD Vertical Timing Signals
      • 110

        Table 4-12. Usable Minimum Values Affecting STN Back Porch Width
      • 111

        Figure 4-4. LCD Panel Power Sequencing
      • 111

        LCD Power Sequencing at Turn-On and Turn-Off
        • 112

          Minimizing a Retained Image On the LCD
        • 113

          Figure 4-5. ALI Simplified Block Diagram
    • 109

      Table 4-11. LH79525 LCD Data Multiplexing
    • 113

      Advanced LCD Interface
      • 114

        ALI Theory of Operation
      • 115

        Table 4-13. CLCDC Register Summary
    • 115

      CLCDC Register Reference
      • 116

        CLCDC Register Descriptions
        • 116

          Table 4-14. TIMING0 Register
        • 116

          Table 4-15. TIMING0 Fields
        • 118

          Table 4-16. TIMING1 Register
        • 118

          Table 4-17. TIMING1 Fields
        • 118

          Vertical Timing Panel Control Register (TIMING1)
        • 120

          Clock and Signal Polarity Control Register (TIMING2)
        • 120

          Table 4-18. TIMING2 Register
        • 120

          Table 4-19. TIMING2 Fields
        • 122

          Table 4-20. UPBASE Register
        • 122

          Table 4-21. UPBASE Fields
        • 122

          Upper Panel Frame Buffer Base Address Register (UPBASE)
        • 123

          Lower Panel Frame Buffer Base Address Register (LPBASE)
        • 123

          Table 4-22. LPBASE Register
        • 123

          Table 4-23. LPBASE Register Fields
        • 124

          Interrupt Enable Register (INTREN)
        • 124

          Table 4-24. INTREN Register
        • 124

          Table 4-25. INTREN Fields
        • 125

          CLCDC Control Register (CTRL)
        • 125

          Table 4-26. CTRL Register
        • 126

          Table 4-27. CTRL Fields
        • 128

          Raw Interrupt Status Register (STATUS)
        • 128

          Table 4-28. STATUS Register
        • 128

          Table 4-29. STATUS Fields
        • 129

          Masked Interrupt Status Register (INTERRUPT)
        • 129

          Table 4-30. INTERRUPT Register
        • 129

          Table 4-31. INTERRUPT Fields
        • 130

          Interrupt Clear Register (INTCLR)
        • 130

          Table 4-32. INTCLR Register
        • 130

          Table 4-33. INTCLR Fields
        • 131

          LCD Upper Panel and Lower Panel Frame Buffer Current Address Register (UPCURR and LPCURR)
        • 131

          Table 4-34. UPCURR Register
        • 131

          Table 4-35. UPCURR Fields
        • 131

          Table 4-36. LPCURR Register
        • 131

          Table 4-37. LCDLPCURR Fields
        • 132

          Bit Color Palette Register (PALETTE)
        • 132

          Table 4-38. PALETTE Register (LH79525 with 12-Bit CLCDC)
        • 132

          Table 4-39. PALETTE Fields (LH79525 with 12-Bit CLCDC)
        • 133

          Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)
        • 133

          Table 4-41. PALETTE Fields (LH79524 with 16-Bit CLCDC)
        • 134

          Table 4-42. ALI Register Summary
        • 134

          Table 4-43. ALISETUP Register
        • 134

          Table 4-44. ALISETUP Fields
      • 134

        ALI Register Reference
        • 135

          Control Register (ALICTRL)
        • 135

          Table 4-45. ALICTRL Register
        • 135

          Table 4-46. ALICTRL Fields
        • 136

          Table 4-47. ALITIMING1 Register
        • 136

          Table 4-48. ALITIMING1 Fields
        • 136

          Timing Delay Register 1 (ALITIMING1)
        • 137

          Table 4-49. ALITIMING2 Register
        • 137

          Table 4-50. ALITIMING2 Fields
        • 137

          Timing Delay Register 2 (ALITIMING2)
      • 138

        STN Horizontal Timing
      • 139

        Figure 4-6. STN Horizontal Timing Diagram
      • 140

        Figure 4-7. STN Vertical Timing Diagram
      • 141

        Figure 4-8. TFT Horizontal Timing Diagram
      • 142

        Figure 4-9. TFT Vertical Timing Diagram
      • 143

        Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram
      • 143

        Figure 4-11. AD-TFT, HR-TFT Vertical Timing Diagram

• 144

  Chapter 5 - Direct Memory Access Controller

  • 144

    Table 5-1. DMA Controller Stream Assignments and Request Priority
    • 146

      Use for SSP and UART
    • 147

      Figure 5-1. Basic DMA Timing
    • 147

      Interrupt, Error, and Status Registers
    • 148

      Table 5-2. DMA Memory Map
    • 148

      Table 5-3. DMA Data Stream Register Summary (One Set of Registers for Each of the Four Data Streams in Table 5-2)

• 149

  Chapter 5 - Direct Memory Access Controller

  • 149

    Table 5-4. SOURCELO Register
  • 149

    Table 5-5. SOURCELO Fields
  • 149

    Table 5-6. SOURCEHI Register
  • 149

    Table 5-7. SOURCEHI Fields
  • 149

    Register Definitions
    • 150

      Destination Base Registers (DESTLO and DESTHI)
    • 150

      Table 5-10. DESTHI Register
    • 150

      Table 5-11. DESTHI Fields
    • 150

      Table 5-8. DESTLO Register
    • 150

      Table 5-9. DESTLO Fields
    • 151

      Maximum Count Register (MAX)
    • 151

      Table 5-12. MAX Register
    • 151

      Table 5-13. MAX Fields
    • 152

      Control Register (CTRL)
    • 152

      Table 5-14. CTRL Register
    • 152

      Table 5-15. CTRL Fields
    • 153

      Table 5-16. DMA Data Width
    • 153

      Table 5-17. DMA Burst Size
    • 154

      Table 5-18. Constraints On CTRL Field Values Based On Stream Type
    • 155

      Current Source Registers (CURSHI and CURSLO)
    • 155

      Table 5-19. CURSHI Register
    • 155

      Table 5-20. CURSHI Fields
    • 155

      Table 5-21. CURSLO Register
    • 155

      Table 5-22. CURSLO Fields
    • 156

      Current Destination Registers (CURDHI and CURDLO)
    • 156

      Table 5-23. CURDHI Register
    • 156

      Table 5-24. CURDHI Fields
    • 156

      Table 5-25. CURDLO Register
    • 156

      Table 5-26. CURDLO Fields
    • 157

      Table 5-27. TCNT Register
    • 157

      Table 5-28. TCNT Fields
    • 157

      Terminal Count Register (TCNT)
    • 158

      Interrupt Mask Register (MASK)
    • 158

      Table 5-29. MASK Register
    • 158

      Table 5-30. MASK Fields
    • 159

      Interrupt Clear Register (CLR)
    • 159

      Table 5-31. CLR Register
    • 159

      Table 5-32. CLR Fields
    • 160

      Table 5-33. STATUS Register
    • 160

      Table 5-34. STATUS Fields

• 162

  Chapter 6 - Ethernet MAC Controller

  • 163

    Figure 6-1. EMAC Block Diagram
    • 163

      Theory of Operation
    • 164

      Operational Overview
      • 165

        Setup
      • 166

        Table 6-1. Receive Buffer Descriptor List
      • 168

        Table 6-2. Transmit Buffer Descriptor List
      • 170

        Receive Block
      • 171

        Table 6-3. Pause Frame Support
      • 172

        Address Checking Block
        • 173

          Broadcast Address
        • 174

          Table 6-4. VLAN Support
        • 174

          Type ID Checking
      • 175

        Initialization
        • 176

          Figure 6-2. Address Matching
        • 177

          Transmit Buffer List
        • 178

          PHY Maintenance
        • 179

          Memory Map
        • 179

          Table 6-5. EMAC Register Summary
        • 181

          Table 6-6. NETCTL Register
        • 181

          Table 6-7. NETCTL Fields
      • 181

        Control, Configuration, and Status Register Definitions
        • 183

          Network Configuration Register (NETCONFIG)
        • 183

          Table 6-8. NETCONFIG Register
        • 183

          Table 6-9. NETCONFIG Fields
        • 185

          Network Status Register (NETSTATUS)
        • 185

          Table 6-10. NETSTATUS Register
        • 185

          Table 6-11. NETSTATUS Fields
        • 186

          Table 6-12. TXSTATUS Register
        • 186

          Table 6-13. TXSTATUS Fields
        • 186

          Transmit Status Register (TXSTATUS)
        • 188

          Receive Buffer Queue Pointer (RXBQP)
        • 188

          Table 6-14. RXBQP Register
        • 188

          Table 6-15. RXBQP Fields
        • 189

          Table 6-16. TXBQP Register
        • 189

          Table 6-17. TXBQP Fields
        • 189

          Transmit Buffer Queue Pointer (TXBQP)
        • 190

          Receive Status Register (RXSTATUS)
        • 190

          Table 6-18. RXSTATUS Register
        • 190

          Table 6-19. RXSTATUS Fields
        • 191

          Interrupt Status Register (INSTATUS)
        • 191

          Table 6-20. INSTATUS Register
        • 191

          Table 6-21. INSTATUS Fields
        • 193

          Interrupt Enable Register (ENABLE)
        • 193

          Table 6-22. ENABLE Register
        • 193

          Table 6-23. ENABLE Fields
        • 194

          Interrupt Disable Register (DISABLE)
        • 194

          Table 6-24. DISABLE Register
        • 194

          Table 6-25. DISABLE Fields
        • 195

          Interrupt Mask Register (MASK)
        • 195

          Table 6-26. MASK Register
        • 195

          Table 6-27. MASK Fields
        • 196

          PHY Maintenance Register (PHYMAINT)
        • 196

          Table 6-28. PHYMAINT Register
        • 196

          Table 6-29. PHYMAINT Fields
        • 197

          Table 6-30. PAUSETIME Register
        • 197

          Table 6-31. PAUSETIME Fields
        • 197

          Table 6-32. TXPAUSEQUAN Register
        • 197

          Table 6-33. TXPAUSEQUAN Fields
        • 198

          Table 6-34. PAUSEFRRX Register
        • 198

          Table 6-35. PAUSEFRRX Fields
      • 198

        Statistics Register Definitions
        • 199

          Frames Transmitted OK (FRMTXOK)
        • 199

          Table 6-36. FRMTXOK Register
        • 199

          Table 6-37. FRMTXOK Fields
        • 199

          Table 6-38. SINGLECOL Register
        • 199

          Table 6-39. SINGLECOL Fields

• 200

  Chapter 6 - Ethernet MAC Controller

  • 200

    Table 6-40. MULTFRM Register
    • 200

      Multiple Collision Frames (MULTFRM)
    • 200

      Table 6-41. MULTFRM Fields
    • 200

      Table 6-42. FRMRXOK Register
    • 200

      Table 6-43. FRMRXOK Fields
    • 201

      Frame Check Sequence Errors (FRCHK)
    • 201

      Table 6-44. FRCHK Register
    • 201

      Table 6-45. FRCHK Fields
    • 201

      Table 6-46. ALIGNERR Register
    • 201

      Table 6-47. ALIGNERR Fields
    • 202

      Deferred Transmission Frames (DEFTXFRM)
    • 202

      Table 6-48. DEFTXFRM Register
    • 202

      Table 6-49. DEFTXFRM Fields
    • 202

      Table 6-50. LATECOL Register
    • 202

      Table 6-51. LATECOL Fields
    • 203

      Excessive Collisions (EXCOL)
    • 203

      Table 6-52. EXCOL Register
    • 203

      Table 6-53. EXCCOL Fields
    • 203

      Table 6-54. TXUNDER Register
    • 203

      Table 6-55. TXUNDER Fields
    • 204

      Carrier Sense Errors (SENSERR)
    • 204

      Table 6-56. SENSERR Register
    • 204

      Table 6-57. SENSERR Fields
    • 205

      Receive Resource Errors (RXRERR)
    • 205

      Table 6-58. RXRERR Register
    • 205

      Table 6-59. RXRERR Fields
    • 205

      Table 6-60. RXOVERR Register
    • 205

      Table 6-61. RXOVERR Fields
    • 206

      Receive Symbol Errors (RXSYMERR)
    • 206

      Table 6-62. RXSYMERR Register
    • 206

      Table 6-63. RXSYMERR Fields
    • 206

      Table 6-64. LENERR Register
    • 206

      Table 6-65. LENERR Fields
    • 207

      Receive Jabbers (RXJAB)
    • 207

      Table 6-66. RXJAB Register
    • 207

      Table 6-67. RXJAB Fields
    • 207

      Table 6-68. UNDERFRM Register
    • 207

      Table 6-69. UNDERFRM Fields
    • 208

      SQE Test Errors (SQERR)
    • 208

      Table 6-70. SQERR Register
    • 208

      Table 6-71. SQERR Fields
    • 208

      Table 6-72. RXLEN Register
    • 208

      Table 6-73. RXLEN Fields
    • 209

      Table 6-74. TXPAUSEFM Register
    • 209

      Table 6-75. TXPAUSEFM Fields
    • 209

      Transmitted Pause Frames (TXPAUSEFM)
      • 210

        Matching Registers
        • 210

          Table 6-76. HASHBOT Register
        • 210

          Table 6-77. HASHBOT Fields
        • 210

          Table 6-78. HASHTOP Register
        • 210

          Table 6-79. HASHTOP Fields
        • 211

          Specific Address 1 Bottom (SPECAD1BOT)
        • 211

          Table 6-80. SPECAD1BOT Register
        • 211

          Table 6-81. SPECAD1BOT Fields
        • 211

          Table 6-82. SPECAD1TOP Register
        • 211

          Table 6-83. SPECAD1TOP Fields
        • 212

          Specific Address 2 Bottom (SPECAD2BOT)
        • 212

          Table 6-84. SPECAD2BOT Register
        • 212

          Table 6-85. SPECAD2BOT Fields
        • 212

          Table 6-86. SPECAD2TOP Register
        • 212

          Table 6-87. SPECAD2TOP Fields
        • 213

          Specific Address 3 Bottom (SPECAD3BOT)
        • 213

          Table 6-88. SPECAD3BOT Register
        • 213

          Table 6-89. SPECAD3BOT Fields
        • 213

          Table 6-90. SPECAD3TOP Register
        • 213

          Table 6-91. SPECAD3TOP Fields
        • 214

          Specific Address 4 Bottom (SPECAD4BOT)
        • 214

          Table 6-92. SPECAD4BOT Register
        • 214

          Table 6-93. SPECAD4BOT Fields
        • 214

          Table 6-94. SPECAD4TOP Register
        • 214

          Table 6-95. SPECAD4TOP Fields
        • 215

          Table 6-96. IDCHK Register
        • 215

          Table 6-97. Typeidcheck Fields
        • 215

          Type ID Checking (IDCHK)

• 216

  Chapter 7 - External Memory Controller

  • 217

    Figure 7-1. External Memory Controller Block Diagram
    • 218

      External Memory Map
    • 219

      Figure 7-2. Automatic Address Shifting
    • 220

      Hardware Design
    • 221

      Figure 7-3. 32-Bit Memory Bank Constructed From 8-Bit Devices
    • 221

      Figure 7-4. 16-Bit Memory Bank Constructed From 8-Bit Devices
    • 221

      Figure 7-5. 8-Bit Memory Bank
    • 222

      Figure 7-6. 32-Bit (Left) and 16-Bit (Right) Memory Banks Constructed From 16-Bit Devices
    • 222

      Figure 7-7. 32-Bit Memory Bank Constructed From a Single 32-Bit Device
    • 223

      Figure 7-8. Typical Memory Connection Diagram
    • 224

      Figure 7-9. Pre-Shifting Routine
    • 224

      Software Design
    • 225

      Table 7-1. Static Memory Configurations
    • 225

      Static Memory Device Selection
      • 226

        Figure 7-10. Static Read Transaction with Zero Wait States
      • 227

        Figure 7-11. Static Read Transaction with Three Wait States
      • 228

        Figure 7-12. Static Write Transaction with Zero Wait States
      • 230

        Figure 7-13. Static Write Transaction with Two Wait States
      • 231

        Bus Turnaround
      • 232

        Extended Wait Transfers
      • 233

        Table 7-2. Boot Configuration for Silicon Version A.0
      • 234

        Figure 7-14. Connection to NAND Flash
      • 235

        General NAND Flash Access
        • 236

          Bit Example Transaction
        • 236

          Figure 7-15. NAND Flash Timing Example
        • 237

          Table 7-5. 32-Bit Wide Data Bus Address Mapping, SDRAM (RBC)
      • 235

        Table 7-4. 16-Bit Address Mapping
    • 237

      Dynamic Memory
      • 238

        Table 7-6. 32-Bit Wide Data Bus Address Mapping, SDRAM (BRC)
      • 240

        Table 7-7. 16-Bit Wide Data Bus Address Mapping, SDRAM (RBC)
      • 241

        Table 7-8. 16-Bit Wide Data Bus Address Mapping, SDRAM (BRC)
      • 242

        Data Mask Signals
      • 242

        Table 7-9. Memory System Examples
      • 243

        Register Reference
      • 243

        Table 7-10. External Memory Controller Register Summary
      • 245

        Register Definitions
        • 245

          Table 7-11. CONTROL Register
        • 245

          Table 7-12. CONTROL Fields
        • 246

          Table 7-13. STATUS Register
        • 246

          Table 7-14. STATUS Fields
        • 247

          Configuration Register (CONFIG)
        • 247

          Table 7-15. CONFIG Register
        • 247

          Table 7-16. CONFIG Fields
        • 248

          Dynamic Memory Control Register (DYNMCTRL)
        • 248

          Table 7-17. DYNMCTRL Register
        • 248

          Table 7-18. DYNMCTRL Fields
        • 249

          Dynamic Refresh Register (DYNMREF)
        • 249

          Table 7-19. DYNMREF Register
        • 249

          Table 7-20. DYNMREF Fields
        • 250

          Dynamic Memory Read Configuration Register (DYNMRCON)
        • 250

          Table 7-21. DYNMRCON Register
        • 250

          Table 7-22. DYNMRCON Fields
        • 251

          Dynamic Precharge Command Period Register (PRECHARGE)
        • 251

          Table 7-23. PRECHARGE Register
        • 251

          Table 7-24. PRECHARGE Fields
        • 252

          Dynamic Memory Active to Precharge Command Period Register (DYNM2PRE)
        • 252

          Table 7-25. DYNM2PRE Register
        • 252

          Table 7-26. DYNM2PRE Fields
        • 253

          Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)
        • 253

          Table 7-27. REFEXIT Register
        • 253

          Table 7-28. REFEXIT Fields
        • 254

          Dynamic Memory Last Data Out to Active Time Register (DOACTIVE)
        • 254

          Table 7-29. DOACTIVE Register
        • 254

          Table 7-30. DOACTIVE Fields
        • 255

          Dynamic Memory Data-In to Active Time Register (DIACTIVE)
        • 255

          Table 7-31. DIACTIVE Register
        • 255

          Table 7-32. DIACTIVE Fields
        • 256

          Dynamic Memory Write Recovery Time Register (DWRT)
        • 256

          Table 7-33. DWRT Register
        • 256

          Table 7-34. DWRT Fields
        • 257

          Dynamic Memory Active to Active Command Period Register (DYNACTCMD)
        • 257

          Table 7-35. DYNACTCMD Register
        • 257

          Table 7-36. DYNACTCMD Fields
        • 258

          Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register (DYNAUTO)
        • 258

          Table 7-37. DYNAUTO Register
        • 258

          Table 7-38. DYNAUTO Fields
        • 259

          Dynamic Memory Exit Self-Refresh to Active Command Time Register (DYNREFEXIT)
        • 259

          Table 7-39. DYNREFEXIT Register
        • 259

          Table 7-40. DYNREFEXIT Fields
        • 260

          Dynamic Memory Active Bank a to Active Bank B Time Register (DYNACTIVEAB)
        • 260

          Table 7-41. DYNACTIVEAB Register
        • 260

          Table 7-42. DYNACTIVEAB Fields
        • 261

          Dynamic Memory Load Mode Register to Active Command Time Register (DYNAMICTMRD)
        • 261

          Table 7-43. DYNAMICTMRD Register
        • 261

          Table 7-44. DYNAMICTMRD Fields
        • 262

          Static Memory Extended Wait Register (WAIT)
        • 262

          Table 7-45. WAIT Register
        • 262

          Table 7-46. WAIT Fields
        • 263

          Dynamic Configuration Register for Ndcs0 and Ndcs1 (Dyncfgx)
        • 263

          Table 7-47. Dyncfgx Register
        • 263

          Table 7-48. Dyncfgx Fields
        • 264

          Table 7-49. Address Mapping
        • 266

          Dynamic Memory RAS and CAS Delay Register for Ndcs0 and Ndcs1 (Dynrascasx)
        • 266

          Table 7-50. Dynrascasx Register
        • 266

          Table 7-51. Dynrascasx Fields
        • 267

          Static Memory Configuration Register (Sconfigx)
        • 267

          Table 7-52. Sconfigx Register
        • 267

          Table 7-53. Sconfigx Fields
        • 269

          Static Memory Write Enable Delay Registers (Swaitwenx)
        • 269

          Table 7-54. Swaitwenx Register
        • 269

          Table 7-55. Swaitwenx Fields
        • 270

          Static Memory Output Enable Delay Registers (Swaitoenx)
        • 270

          Table 7-56. Swaitoenx Register
        • 270

          Table 7-57. Swaitoenx Fields
        • 271

          Static Memory Read Delay Registers (Swaitrdx)
        • 271

          Table 7-58. Swaitrdx Register
        • 271

          Table 7-59. Swaitrdx Fields
        • 272

          Table 7-60. Swaitpagex Register
        • 272

          Table 7-61. Swaitpagex Fields
        • 273

          Static Memory Write Delay Registers (Swaitwrx)
        • 273

          Table 7-62. Swaitwrx Register
        • 273

          Table 7-63. Swaitwrx Fields
        • 274

          Static Memory Turn Around Delay Registers (Sturnx)
        • 274

          Table 7-64. Sturnx Register
        • 274

          Table 7-65. Sturnx Fields

• 275

  Chapter 8 - General Purpose Input/Output

  • 275

    Table 8-1. GPIO Ports
  • 275

    Theory of Operation
  • 276

    Table 8-2. LH79524 GPIO Multiplexing
  • 279

    Table 8-3. LH79525 GPIO Multiplexing
  • 281

    Table 8-4. GPIO Port Memory Map
  • 281

    Register Reference
    • 282

      Register Descriptions
      • 282

        Table 8-5. P1Drx Register
      • 282

        Table 8-6. P1Drx Fields
      • 283

        Port B/D/F/H/J/L/N Data Register (P2Drx)
      • 283

        Table 8-7. P2Drx Register
      • 283

        Table 8-8. P2Drx Fields
      • 284

        Port A/C/E/G/I/K Data Direction Register (P1Ddrx)
      • 284

        Table 8-10. P1Ddrx Fields
      • 284

        Table 8-9. P1Ddrx Register
      • 285

        Port B/D/F/H/L/N Data Direction Register
      • 285

        Table 8-11. P2Ddrx Register
      • 285

        Table 8-12. P2Ddrx Register Definitions

• 287

  Chapter 9 - I 2 C Module

  • 288

    Figure 9-2. I 2 C Bus Protocol
    • 288

      Theory of Operation
    • 290

      Interrupt Handling
    • 291

      Slave Mode
    • 292

      Register Reference
    • 292

      Table 9-3. I 2 C Register Summary
    • 293

      Register Definitions
    • 293

      Table 9-4. ICCON Register
    • 293

      Table 9-5. ICCON Fields
    • 294

      Table 9-6. ICSAR Register
    • 294

      Table 9-7. ICSAR Fields
    • 295

      Table 9-10. ICDATA Register
    • 295

      Table 9-11. ICDATA Fields
    • 295

      Table 9-8. ICUSAR Register
    • 295

      Table 9-9. ICUSAR Fields
    • 296

      Table 9-12. ICHCNT Register
    • 296

      Table 9-13. ICHCNT Fields
    • 296

      Table 9-14. ICLCNT Register
    • 296

      Table 9-15. ICLCNT Fields
    • 297

      Table 9-16. ICSTAT Register
    • 297

      Table 9-17. ICSTAT Fields
    • 301

      Figure 10-2. TI SSP Frame Format
    • 301

      Theory of Operation
    • 302

      Driving/Latching Edges
    • 302

      Figure 10-4. Driving/Latching Diagram
    • 303

      Figure 10-5. I 2 S Master Mode Transmission Block Diagram
    • 303

      Figure 10-6. I 2 S Master Mode Transmission Timing Diagram

• 303

  Chapter 10 - I 2 S Converter

  • 303

    Transmission
  • 304

    Figure 10-7. I 2 S Slave Mode Transmission Block Diagram
  • 305

    Figure 10-8. I 2 S Slave Mode Transmission Timing Diagram
  • 305

    Reception
    • 307

      Slave Mode Reception
    • 308

      Suppression of SSPFSSIN
  • 309

    Interrupts
    • 310

      Receive Interrupt
    • 311

      Memory Map
    • 312

      Table 10-2. CTRL Register
    • 312

      Table 10-3. CTRL Register Definitions
    • 312

      Register Descriptions
      • 313

        Table 10-4. WSINV Functionality
      • 314

        Status Register (STAT)
      • 314

        Table 10-5. STAT Register
      • 314

        Table 10-6. STAT Register Definitions
      • 315

        Interrupt Mask Set or Clear Register (IMSC)
      • 315

        Table 10-7. IMSC Register
      • 315

        Table 10-8. IMSC Register Definitions
      • 316

        Raw Interrupt Status Register (RIS)
      • 316

        Table 10-10. RIS Register Definitions
      • 316

        Table 10-9. RIS Register
      • 317

        Masked Interrupt Status Register (MIS)
      • 317

        Table 10-11. MIS Register
      • 317

        Table 10-12. MIS Register Definitions
      • 318

        Interrupt Clear Register (ICR)
      • 318

        Table 10-13. ICR Register
      • 318

        Table 10-14. ICR Register Definitions
      • 320

        Table 11-1. IOCON Register Summary
    • 320

      Memory Map
    • 322

      Table 11-2. MUXCTL1 Register
    • 322

      Table 11-3. MUXCTL1 Fields
    • 322

      Register Definitions
      • 323

        Resistor Configuration Control 1 Register (RESCTL1)
      • 323

        Table 11-4. RESCTL1 Register
      • 323

        Table 11-5. RESCTL1 Fields
      • 324

        Multiplexing Control 3 Register (MUXCTL3)
      • 324

        Table 11-6. MUXCTL3 Register
      • 324

        Table 11-7. MUXCTL3 Fields
      • 324

        Table 11-8. RESCTL3 Register
      • 324

        Table 11-9. RESCTL3 Fields
      • 325

        Multiplexing Control 4 Register (MUXCTL4)
      • 325

        Table 11-10. MUXCTL4 Register
      • 325

        Table 11-11. MUXCTL4 Fields
      • 326

        Resistor Configuration Control 4 Register (RESCTL4)
      • 326

        Table 11-12. RESCTL4 Register
      • 326

        Table 11-13. RESCTL4 Fields
      • 327

        Multiplexing Control 5 Register (MUXCTL5)
      • 327

        Table 11-14. MUXCTL5 Register
      • 327

        Table 11-15. MUXCTL5 Fields
      • 328

        Resistor Configuration Control 5 Register (RESCTL5)
      • 328

        Table 11-16. RESCTL5 Register
      • 328

        Table 11-17. RESCTL5 Fields
      • 330

        Multiplexing Control 6 Register (MUXCTL6)
      • 330

        Table 11-18. MUXCTL6 Register
      • 330

        Table 11-19. MUXCTL6 Fields
      • 331

        Resistor Configuration Control 6 Register (RESCTL6)
      • 331

        Table 11-20. RESCTL6 Register
      • 331

        Table 11-21. RESCTL6 Fields
      • 332

        Multiplexing Control 7 Register (MUXCTL7)
      • 332

        Table 11-22. MUXCTL7 Register
      • 332

        Table 11-23. MUXCTL7 Fields
      • 334

        Resistor Configuration Control 7 Register (RESCTL7)
      • 334

        Table 11-24. RESCTL7 Register
      • 334

        Table 11-25. RESCTL7 Fields
      • 336

        Multiplexing Control 10 Register (MUXCTL10)
      • 336

        Table 11-26. MUXCTL10 Register
      • 336

        Table 11-27. MUXCTL10 Fields
      • 338

        Resistor Configuration Control 10 Register (RESCTL10)
      • 338

        Table 11-28. RESCTL10 Register
      • 338

        Table 11-29. RESCTL10 Fields
      • 340

        Multiplexing Control 11 Register (MUXCTL11)
      • 340

        Table 11-30. MUXCTL11 Register
      • 340

        Table 11-31. MUXCTL11 Fields
      • 342

        Resistor Configuration Control 11 Register (RESCTL11)
      • 342

        Table 11-32. RESCTL11 Register
      • 342

        Table 11-33. RESCTL11 Fields
      • 344

        Multiplexing Control 12 Register (MUXCTL12)
      • 344

        Table 11-34. MUXCTL12 Register
      • 344

        Table 11-35. MUXCTL12 Fields
      • 345

        Resistor Configuration Control 12 Register (RESCTL12)
      • 345

        Table 11-36. RESCTL12 Register
      • 345

        Table 11-37. RESCTL12 Fields
      • 347

        Resistor Configuration Control 13 Register (RESCTL13)
      • 347

        Table 11-38. RESCTL13 Register
      • 347

        Table 11-39. RESCTL13 Fields
      • 348

        Multiplexing Control 14 Register (MUXCTL14)
      • 348

        Table 11-40. MUXCTL14 Register
      • 348

        Table 11-41. MUXCTL14 Fields
      • 350

        Multiplexing Control 15 Register (MUXCTL15)
      • 350

        Table 11-42. MUXCTL15 Register
      • 350

        Table 11-43. MUXCTL15 Fields
      • 350

        Table 11-44. RESCTL15 Register
      • 350

        Table 11-45. RESCTL15 Fields
      • 351

        Resistor Configuration Control 17 Register (RESCTL17)
      • 351

        Table 11-46. RESCTL17 Register
      • 351

        Table 11-47. RESCTL17 Fields
      • 352

        Multiplexing Control 19 Register (MUXCTL19)
      • 352

        Table 11-48. MUXCTL19 Register
      • 352

        Table 11-49. MUXCTL19 Fields
      • 354

        Resistor Configuration Control 19 Register (RESCTL19)
      • 354

        Table 11-50. RESCTL19 Register
      • 354

        Table 11-51. RESCTL19 Fields
      • 356

        Multiplexing Control 20 Register (MUXCTL20)
      • 356

        Table 11-52. MUXCTL20 Register
      • 356

        Table 11-53. MUXCTL20 Fields
      • 358

        Resistor Configuration Control 20 Register (RESCTL20)
      • 358

        Table 11-54. RESCTL20 Register
      • 358

        Table 11-55. RESCTL20 Fields
      • 360

        Multiplexing Control 21 Register (MUXCTL21)
      • 360

        Table 11-56. MUXCTL21 Register
      • 360

        Table 11-57. MUXCTL21 Fields
      • 361

        Resistor Configuration Control 21 Register (RESCTL21)
      • 361

        Table 11-58. RESCTL21 Register
      • 361

        Table 11-59. RESCTL21 Fields
      • 362

        Multiplexing Control 22 Register (MUXCTL22)
      • 362

        Table 11-60. MUXCTL22 Register
      • 362

        Table 11-61. MUXCTL22 Fields
      • 364

        Resistor Configuration Control 22 Register (RESCTL22)
      • 364

        Table 11-62. RESCTL22 Register
      • 364

        Table 11-63. RESCTL22 Fields
      • 366

        Multiplexing Control 23 Register (MUXCTL23)
      • 366

        Table 11-64. MUXCTL23 Register
      • 366

        Table 11-65. MUXCTL23 Fields
      • 368

        Resistor Configuration Control 23 Register (RESCTL23)
      • 368

        Table 11-66. RESCTL23 Register
      • 368

        Table 11-67. RESCTL23 Fields
      • 370

        Multiplexing Control 24 Register (MUXCTL24)
      • 370

        Table 11-68. MUXCTL24 Register
      • 370

        Table 11-69. MUXCTL24 Fields
      • 371

        Resistor Configuration Control 24 Register (RESCTL24)
      • 371

        Table 11-70. RESCTL24 Register
      • 371

        Table 11-71. RESCTL24 Fields
      • 372

        Multiplexing Control 25 Register (MUXCTL25)
      • 372

        Table 11-72. MUXCTL25 Register
      • 373

        Table 11-73. MUXCTL25 Fields
      • 375

        Figure 12-1. RTC Block Diagram
  • 375

    Theory of Operation
    • 376

      Configuring the RTC for Use
    • 377

      Table 12-1. RTC Register Summary
    • 377

      Table 12-2. DR Register
    • 377

      Table 12-3. DR Fields
  • 377

    Register Reference
    • 378

      Match Register (MR)
    • 378

      Table 12-4. MR Register
    • 378

      Table 12-5. MR Fields
    • 378

      Table 12-6. LR Register
    • 378

      Table 12-7. LR Fields
    • 379

      Control Register (CR)
    • 379

      Table 12-10. IMSC Register
    • 379

      Table 12-11. IMSC Fields
    • 379

      Table 12-8. CR Register
    • 379

      Table 12-9. CR Fields
    • 380

      Raw Interrupt Status Register (RIS)
    • 380

      Table 12-12. RIS Register
    • 380

      Table 12-13. RIS Fields
    • 380

      Table 12-14. MIS Register
    • 380

      Table 12-15. MIS Fields
    • 381

      Interrupt Clear Register (ICR)
    • 381

      Table 12-16. ICR Register
    • 381

      Table 12-17. ICR Fields
    • 383

      Figure 13-1. RCPC Block Diagram
  • 383

    Theory of Operation
    • 384

      System PLL and USB PLL Reset
      • 385

        Figure 13-2. USB Clock Divider Chain
      • 385

        Peripheral Block Clocks
      • 386

        Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies
      • 387

        Table 13-2. Clock and Enable States for Different Power Modes
      • 388

        Stop2 Mode
      • 389

        Table 13-3. RCPC Register Summary
  • 389

    Register Reference
    • 390

      Control Register (CTRL)
    • 390

      Table 13-4. CTRL Register
    • 390

      Table 13-5. CTRL Fields
    • 391

      Identification Register (CHIPID)
    • 391

      Table 13-6. CHIPID Register
    • 391

      Table 13-7. CHIPID Fields
    • 392

      Figure 13-3. Remap = 0B00
    • 392

      Remap Control Register (REMAP)
    • 392

      Table 13-8. REMAP Register
    • 392

      Table 13-9. REMAP Fields
    • 393

      Figure 13-4. Remap = 0B01
    • 393

      Figure 13-5. Remap = 0B10
    • 394

      Figure 13-6. Remap = 0B11
    • 395

      Software Reset Register (SOFTRESET)
    • 395

      Table 13-10. SOFTRESET Register
    • 395

      Table 13-11. SOFTRESET Fields
    • 396

      Reset Status Register (RSTSTATUS)
    • 396

      Table 13-12. RSTSTATUS Register
    • 396

      Table 13-13. RSTSTATUS Fields
    • 397

      Reset Status Clear Register (RSTSTATUSCLR)
    • 397

      Table 13-14. RSTSTATUSCLR Register
    • 397

      Table 13-15. RSTSTATUSCLR Fields
    • 398

      System Clock Prescaler Register (SYSCLKPRE)
    • 398

      Table 13-16. SYSCLKPRE Register
    • 398

      Table 13-17. SYSCLKPRE Fields
    • 398

      Table 13-18. SYSCLKPRE Register Values
    • 399

      CPU Clock Prescaler Register (CPUCLKPRE)
    • 399

      Table 13-19. CPUCLKPRE Register
    • 399

      Table 13-20. CPUCLKPRE Fields
    • 399

      Table 13-21. CPUCLKPRE Register Values
    • 400

      Peripheral Clock Control Register 0 (PCLKCTRL0)
    • 400

      Table 13-22. PCLKCTRL0 Register
    • 400

      Table 13-23. PCLKCTRL0 Fields
    • 401

      Peripheral Clock Control Register 1 (PCLKCTRL1)
    • 401

      Table 13-24. PCLKCTRL1 Register
    • 401

      Table 13-25. PCLKCTRL1 Fields
    • 402

      AHB Clock Control Register (AHBCLKCTRL)
    • 402

      Table 13-26. AHBCLKCTRL Register
    • 402

      Table 13-27. AHBCLKCTRL Fields
    • 403

      Peripheral Clock Select Register 0 (PCLKSEL0)
    • 403

      Table 13-28. PCLKSEL0 Register
    • 403

      Table 13-29. PCLKSEL0 Fields
    • 404

      Peripheral Clock Select Register 1 (PCLKSEL1)
    • 404

      Table 13-30. PCLKSEL1 Register
    • 404

      Table 13-31. PCLKSEL1 Fields
    • 405

      Silicon Revision Register (SILICONREV)
    • 405

      Table 13-32. SILICONREV Register
    • 405

      Table 13-33. SILICONREV Fields
    • 406

      LCD Clock Prescaler Register (LCDPRE)
    • 406

      Table 13-34. LCDPRE Register
    • 406

      Table 13-35. LCDPRE Fields
    • 406

      Table 13-36. LCDPRE Register Values
    • 407

      SSP Clock Prescaler Register (SSPPRE)
    • 407

      Table 13-37. SSPPRE Register
    • 407

      Table 13-38. SSPPRE Fields
    • 407

      Table 13-39. SSPPRE Register Values
    • 408

      ADC Clock Prescaler Register (ADCPRE)
    • 408

      Table 13-40. ADCPRE Register
    • 408

      Table 13-41. ADCPRE Fields
    • 408

      Table 13-42. ADCPRE Register Values
    • 409

      Table 13-43. USBPRE Register
    • 409

      Table 13-44. USBPRE Fields
    • 409

      Table 13-45. USBPRE Register Values
    • 409

      USB Clock Prescaler Register (USBPRE)
    • 410

      External Interrupt Configuration Register (INTCONFIG)
    • 410

      Table 13-46. INTCONFIG Register
    • 410

      Table 13-47. INTCONFIG Fields
    • 412

      External Interrupt Clear Register (INTCLR)
    • 412

      Table 13-48. INTCLR Register
    • 412

      Table 13-49. INTCLR Fields
    • 413

      Core Clock Configuration Register (CORECONFIG)
    • 413

      Table 13-50. CORECONFIG Register
    • 413

      Table 13-51. CORECONFIG Fields
    • 414

      System PLL Control Register (SYSPLLCTL)
    • 414

      Table 13-52. SYSPLLCTL Register
    • 414

      Table 13-53. SYSPLLCTL Fields
    • 415

      Table 13-54. USBPLLCTL Register
    • 415

      Table 13-55. USBPLLCTL Fields
    • 415

      USB PLL Control Register (USBPLLCTL)
  • 416

    Theory of Operation
    • 417

      Table 14-1. Feature Comparison
    • 418

      Figure 14-1. SSP Timing Waveform Parameters
    • 418

      Timing Waveforms
    • 419

      Figure 14-2. Motorola SPI Frame Format (Continuous Transfer)
    • 420

      Figure 14-4. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
    • 420

      Figure 14-5. Texas Instruments Synchronous Serial Frame Format (Continuous Transfers)
    • 421

      Figure 14-6. Microwire Frame Format (Single Transfer)
    • 421

      National Semiconductor Frame Format
    • 422

      Clock Generation
    • 422

      Figure 14-7. Microwire Frame Format (Continuous Transfers)