Sharp LH79525 Manuals

Manuals and User Guides for Sharp LH79525. We have 1 Sharp LH79525 manual available for free PDF download: User Manual

Sharp LH79525 User Manual (555 pages)

Brand: Sharp | Category: Controller | Size: 9.24 MB

Table Of Contents4

Overview41

Version43

Table 1-1. Lh79524/lh79525 Differences44

Figure 1-1. Lh79524/lh79525 Block Diagram45

Table 1-2. Clock Descriptions47

Figure 1-2. Standard Clocking Modes49

Figure 1-3. Fastbus Clocking Mode50

Table 1-3. Port C Settings For Boot51

Figure 1-4. Reset Circuit For Tap Controller52

Hardware Requirements At Reset53

Active Pull Ups54

Ahb Bus Master Priority And Arbitration55

Table 1-5. Ahb Memory Mapping56

Table 1-8. Internal Sram Memory Section Mapping57

Table 1-11. Primary Ahb Peripheral Register Mapping58

Table 1-12. Apb Peripheral Register Mapping59

Instruction And Data Cache60

Theory Of Operation61

Figure 2-1. Adc Block Diagram62

Bias-and-control Network63

Figure 2-2. Bias-and-control Network Block Diagram64

Clock Generator65

Figure 2-4. Example Of A 4-bit Sar Adc Operation66

Battery Control Feature67

Timing Formulas68

Pen Interrupt69

Table 2-4. In + Mux Definition72

Low Word Register (lw)73

Results Register (rr)74

Interrupt Mask Register (im)75

Power Configuration Register (pc)76

Table 2-13. Touch Screen Controller Power Modes77

General Configuration Register (gc)78

General Status Register (gs)79

Interrupt Status Register (is)80

Fifo Status Register (fs)81

Control Bank Registers82

Idle High Word Register (ihwctrl)83

Idle Low Word Register (ilwctrl)84

Masked Interrupt Status Register (mis)85

Interrupt Clear Register (ic)86

Figure 3-1. Boot Controller Block Diagram87

Table 3-1. Boot Configuration For Silicon Version A.089

Nand Flash Operation90

Nand Flash Hardware Design91

Table 3-5. Supported Devices92

Booting From Uart93

Ncs1 Override Register (cs1ov)95

External Peripheral Mapping Register (epm)96

Introduction97

Lcd Panel Architecture98

Clcdc Features99

Figure 4-3. Color Lcd Controller Block Diagram100

Supported Displays And Panels101

Pixel Serializer102

Table 4-3. Frame Buffer Pixel Storage Format [15:0]103

Palette Ram104

Grayscale Algorithm105

Table 4-6. Supported Tft, Hr-tft, And Ad-tft Lcd Panels106

Table 4-9. Color Stn Intensities From Gray-scale Modulation107

Lcd Data Multiplexing108

Lcd Interface Timing Signals109

Lcd Vertical Timing Signals110

Lcd Power Sequencing At Turn-on And Turn-off111

Minimizing A Retained Image On The Lcd112

Advanced Lcd Interface113

Ali Theory Of Operation114

Clcdc Register Reference115

Clcdc Register Descriptions116

Vertical Timing Panel Control Register (timing1)118

Clock And Signal Polarity Control Register (timing2)120

Upper Panel Frame Buffer Base Address Register (upbase)122

Lower Panel Frame Buffer Base Address Register (lpbase)123

Interrupt Enable Register (intren)124

Clcdc Control Register (ctrl)125

Table 4-27. Ctrl Fields126

Raw Interrupt Status Register (status)128

Masked Interrupt Status Register (interrupt)129

Interrupt Clear Register (intclr)130

Lcd Upper Panel And Lower Panel Frame Buffer Current Address Register (upcurr And Lpcurr)131

Bit Color Palette Register (palette)132

Table 4-40. Palette Register (lh79524 With 16-bit Clcdc)133

Ali Register Reference134

Control Register (alictrl)135

Timing Delay Register 1 (alitiming1)136

Timing Delay Register 2 (alitiming2)137

Stn Horizontal Timing138

Figure 4-6. Stn Horizontal Timing Diagram139

Figure 4-7. Stn Vertical Timing Diagram140

Figure 4-8. Tft Horizontal Timing Diagram141

Figure 4-9. Tft Vertical Timing Diagram142

Figure 4-10. Ad-tft, Hr-tft Horizontal Timing Diagram143

Table 5-1. Dma Controller Stream Assignments And Request Priority144

Use For Ssp And Uart146

Interrupt, Error, And Status Registers147

Memory Map148

Destination Base Registers (destlo And Desthi)150

Maximum Count Register (max)151

Control Register (ctrl)152

Table 5-16. Dma Data Width153

Table 5-18. Constraints On Ctrl Field Values Based On Stream Type154

Current Source Registers (curshi And Curslo)155

Current Destination Registers (curdhi And Curdlo)156

Terminal Count Register (tcnt)157

Interrupt Mask Register (mask)158

Interrupt Clear Register (clr)159

Status Register (status)160

Operational Overview164

Setup165

Table 6-1. Receive Buffer Descriptor List166

Transmit Buffer168

Receive Block170

Pause Frame Support171

Address Checking Block172

Broadcast Address173

Type Id Checking174

Initialization175

Figure 6-2. Address Matching176

Transmit Buffer List177

Phy Maintenance178

Control, Configuration, And Status Register Definitions181

Network Configuration Register (netconfig)183

Network Status Register (netstatus)185

Transmit Status Register (txstatus)186

Receive Buffer Queue Pointer (rxbqp)188

Transmit Buffer Queue Pointer (txbqp)189

Receive Status Register (rxstatus)190

Interrupt Status Register (instatus)191

Interrupt Enable Register (enable)193

Interrupt Disable Register (disable)194

Phy Maintenance Register (phymaint)196

Pause Time Register (pausetime)197

Statistics Register Definitions198

Frames Transmitted Ok (frmtxok)199

Multiple Collision Frames (multfrm)200

Frame Check Sequence Errors (frchk)201

Deferred Transmission Frames (deftxfrm)202

Excessive Collisions (excol)203

Carrier Sense Errors (senserr)204

Receive Resource Errors (rxrerr)205

Receive Symbol Errors (rxsymerr)206

Receive Jabbers (rxjab)207

Sqe Test Errors (sqerr)208

Transmitted Pause Frames (txpausefm)209

Matching Registers210

Specific Address 1 Bottom (specad1bot)211

Specific Address 2 Bottom (specad2bot)212

Specific Address 3 Bottom (specad3bot)213

Specific Address 4 Bottom (specad4bot)214

Type Id Checking (idchk)215

Figure 7-1. External Memory Controller Block Diagram217

External Memory Map218

Figure 7-2. Automatic Address Shifting219

Hardware Design220

Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices221

Figure 7-7. 32-bit Memory Bank Constructed From A Single 32-bit Device222

Figure 7-8. Typical Memory Connection Diagram223

Software Design224

Static Memory Device Selection225

Figure 7-10. Static Read Transaction With Zero Wait States226

Figure 7-11. Static Read Transaction With Three Wait States227

Figure 7-12. Static Write Transaction With Zero Wait States228

Figure 7-13. Static Write Transaction With Two Wait States230

Bus Turnaround231

Extended Wait Transfers232

Table 7-2. Boot Configuration For Silicon Version A.0233

Figure 7-14. Connection To Nand Flash234

General Nand Flash Access235

Bit Example Transaction236

Dynamic Memory237

Table 7-6. 32-bit Wide Data Bus Address Mapping, Sdram (brc)238

Table 7-7. 16-bit Wide Data Bus Address Mapping, Sdram (rbc)240

Table 7-8. 16-bit Wide Data Bus Address Mapping, Sdram (brc)241

Data Mask Signals242

Configuration Register (config)247

Dynamic Memory Control Register (dynmctrl)248

Dynamic Refresh Register (dynmref)249

Dynamic Memory Read Configuration Register (dynmrcon)250

Dynamic Precharge Command Period Register (precharge)251

Dynamic Memory Active To Precharge Command Period Register (dynm2pre)252

Dynamic Memory Self-refresh Exit Time Register (refexit)253

Dynamic Memory Last Data Out To Active Time Register (doactive)254

Dynamic Memory Data-in To Active Time Register (diactive)255

Dynamic Memory Write Recovery Time Register (dwrt)256

Dynamic Memory Active To Active Command Period Register (dynactcmd)257

Dynamic Memory Auto-refresh Period, And Auto-refresh To Active Command Period Register (dynauto)258

Dynamic Memory Exit Self-refresh To Active Command Time Register (dynrefexit)259

Dynamic Memory Active Bank A To Active Bank B Time Register (dynactiveab)260

Dynamic Memory Load Mode Register To Active Command Time Register (dynamictmrd)261

Static Memory Extended Wait Register (wait)262

Dynamic Configuration Register For Ndcs0 And Ndcs1 (dyncfgx)263

Table 7-49. Address Mapping264

Dynamic Memory Ras And Cas Delay Register For Ndcs0 And Ndcs1 (dynrascasx)266

Static Memory Configuration Register (sconfigx)267

Static Memory Write Enable Delay Registers (swaitwenx)269

Static Memory Output Enable Delay Registers (swaitoenx)270

Static Memory Read Delay Registers (swaitrdx)271

Table 7-60. Swaitpagex Register272

Static Memory Write Delay Registers (swaitwrx)273

Static Memory Turn Around Delay Registers (sturnx)274

Multiplexing276

Table 8-3. Lh79525 Gpio Multiplexing279

Port B/d/f/h/j/l/n Data Register (p2drx)283

Port A/c/e/g/i/k Data Direction Register (p1ddrx)284

Port B/d/f/h/l/n Data Direction Register285

Interrupt Handling290

Slave Mode291

Table 9-6. Icsar Register294

Table 9-8. Icusar Register295

Table 9-12. Ichcnt Register296

Table 9-16. Icstat Register297

Driving/latching Edges302

Transmission303

Slave Mode Transmission304

Reception305

Slave Mode Reception307

Suppression Of Sspfssin308

Interrupts309

Receive Interrupt310

Table 10-4. Wsinv Functionality313

Status Register (stat)314

Interrupt Mask Set Or Clear Register (imsc)315

Raw Interrupt Status Register (ris)316

Interrupt Clear Register (icr)318

Resistor Configuration Control 1 Register (resctl1)323

Multiplexing Control 3 Register (muxctl3)324

Multiplexing Control 4 Register (muxctl4)325

Resistor Configuration Control 4 Register (resctl4)326

Multiplexing Control 5 Register (muxctl5)327

Resistor Configuration Control 5 Register (resctl5)328

Multiplexing Control 6 Register (muxctl6)330

Resistor Configuration Control 6 Register (resctl6)331

Multiplexing Control 7 Register (muxctl7)332

Resistor Configuration Control 7 Register (resctl7)334

Multiplexing Control 10 Register (muxctl10)336

Resistor Configuration Control 10 Register (resctl10)338

Multiplexing Control 11 Register (muxctl11)340

Resistor Configuration Control 11 Register (resctl11)342

Multiplexing Control 12 Register (muxctl12)344

Resistor Configuration Control 12 Register (resctl12)345

Resistor Configuration Control 13 Register (resctl13)347

Multiplexing Control 14 Register (muxctl14)348

Multiplexing Control 15 Register (muxctl15)350

Resistor Configuration Control 17 Register (resctl17)351

Multiplexing Control 19 Register (muxctl19)352

Resistor Configuration Control 19 Register (resctl19)354

Multiplexing Control 20 Register (muxctl20)356

Resistor Configuration Control 20 Register (resctl20)358

Multiplexing Control 21 Register (muxctl21)360

Resistor Configuration Control 21 Register (resctl21)361

Multiplexing Control 22 Register (muxctl22)362

Resistor Configuration Control 22 Register (resctl22)364

Multiplexing Control 23 Register (muxctl23)366

Resistor Configuration Control 23 Register (resctl23)368

Multiplexing Control 24 Register (muxctl24)370

Resistor Configuration Control 24 Register (resctl24)371

Multiplexing Control 25 Register (muxctl25)372

Configuring The Rtc For Use376

Match Register (mr)378

Control Register (cr)379

System Pll And Usb Pll Reset384

Peripheral Block Clocks385

Table 13-1. Lh79524/lh79525 Clocks And Maximum Frequencies386

Power Modes387

Stop2 Mode388

Identification Register (chipid)391

Remap Control Register (remap)392

Figure 13-4. Remap = 0b01393

Figure 13-6. Remap = 0b11394

Software Reset Register (softreset)395

Reset Status Register (rststatus)396

Reset Status Clear Register (rststatusclr)397

System Clock Prescaler Register (sysclkpre)398

Cpu Clock Prescaler Register (cpuclkpre)399

Peripheral Clock Control Register 0 (pclkctrl0)400

Peripheral Clock Control Register 1 (pclkctrl1)401

Ahb Clock Control Register (ahbclkctrl)402

Peripheral Clock Select Register 0 (pclksel0)403

Peripheral Clock Select Register 1 (pclksel1)404

Silicon Revision Register (siliconrev)405

Lcd Clock Prescaler Register (lcdpre)406

Ssp Clock Prescaler Register (ssppre)407

Adc Clock Prescaler Register (adcpre)408

Usb Clock Prescaler Register (usbpre)409

External Interrupt Configuration Register (intconfig)410

External Interrupt Clear Register (intclr)412

Core Clock Configuration Register (coreconfig)413

System Pll Control Register (syspllctl)414

Usb Pll Control Register (usbpllctl)415

Table 14-1. Feature Comparison417

Timing Waveforms418

Motorola Spi Frame Format419

Texas Instruments Frame Format420

National Semiconductor Frame Format421

Clock Generation422

Transmit Interrupt423

Control Register 1 (ctrl1)427

Data Register – Receive/transmit Fifo Register (dr)428

Status Register (sr)429

Clock Prescale Register (cpsr)430

Interrupt Mask Set And Clear Register (imsc)431

Dma Control Register (dcr)435

Counter Clear Upon Compare Match438

Capture Signal Sampling439

Timer Interrupts440

Timer 0 Compare/capture Control Register (cmp_cap_ctrl0)443

Timer 0 Interrupt Control Register (inten0)445

Timer 0 Status Register (status0)446

Timer 0 Counter Register (cnt0)447

Timer 0 Compare Registers (t0cmpn)448

Timer 0 Capture Registers (capn)449

Timer 1 Control Register (ctrl1)450

Timer 1 Interrupt Control Register (inten1)452

Timer 1 Status Register (status1)453

Timer 1 Counter Register (cnt1)454

Timer 1 Compare Registers (t1cmpn)455

Timer 1 Capture Registers (t1capn)456

Timer 2 Control Register (ctrl2)457

Timer 2 Interrupt Control Register (inten2)459

Timer 2 Status Register (status2)460

Timer 2 Counter Register (cnt2)461

Timer 2 Compare Registers (t2cmpn)462

Timer 2 Capture Registers (t2capn)463

Transmitting Data466

Nine-bit Mode467

On-chip Dma Capabilities468

Hardware Flow Control469

Receive Status/error Clear Register (uartrsr/uartecr)472

Table 16-8. Uartrsr/uartecr Register (read Operations)473

Flag Register (uartfr)474

Irda Low-power Counter Register (uartilpr)475

Integer Baud Rate Divisor Register (uartibrd)476

Fractional Baud Rate Divisor Register (uartfbrd)477

Line Control Register (uartlcr_h)478

Table 16-21. Truth Table For 9bit, Sps, Eps, And Pen Bits479

Uart Control Register (uartcr)480

Interrupt Fifo Level Select Register (uartifls)482

Interrupt Mask Set/clear Register (uartimsc)483

Raw Interrupt Status Register (uartris)485

Masked Interrupt Status Register (uartmis)487

Interrupt Clear Register (uarticr)489

Uart0 Dma Control Register (dmactrl)490

Endpoints492

Isochronous Endpoints493

Dma Interface494

Dma Operation495

Dma Mode 1: Out Endpoints496

Dma Mode 1: In Endpoints497

Power Management Register (pmr)501

Interrupt Register For Endpoint 0, 1, 2, And 3 (iir)502

Interrupt Register For Out Endpoint 1 And 2 (oir)503

Interrupt Register For Common Usb Interrupts (uir)504

In Interrupt Enable Register (iie)505

Out Interrupt Enable Register (oie)506

Interrupt Enable Register (uie)507

Frame Number Registers (framex)508

Indexed Registers509

In Maximum Packet Size Register (inmaxp)510

Control Status Register For Ep 0 (csr0)511

Control Status Register 1 For In Ep 1, 2, And 3 (incsr1)513

Control Status Register 2 For In Ep 1, 2, And 3 (incsr2)515

Out Maximum Packet Size Register Ep 1 And 2 (outmaxp)516

Control Status Register 1 For Out Ep1 And Ep2 (outscsr1)517

Control Status Register 2 For Out Ep1 And Ep 2 (outcsr2)519

Count 0 Register (outcount0)520

Out Count 2 Register (outcount2)521

Pending Dma Interrupts Register (intr)522

Dma Channel X Control Register (cntlx)523

Dma Channel X Ahb Memory Address Register524

Vic Interrupt Listing526

Vectored Interrupts527

Clearing Interrupts528

Fiq Status Register (fiqstatus)531

Interrupt Select Register (intselect)532

Interrupt Enable Clear Register (intenclear)533

Software Interrupt Register (softint)534

Software Interrupt Clear Register (softintclear)535

Vector Address Register (vectaddr)536

Vector Address Registers (vectaddrx)537

Vector Control Registers (vectctrlx)538

Interrupt Test Output Register (itop)539

Figure 19-1. Watchdog Timer Block Diagram541

Wdt Operation Details542

Counter Reset Register (rst)545

Current Watchdog Count Registers (count[3:0])547

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Sharp LH79525 Manuals

Manuals and User Guides for Sharp LH79525. We have 1 Sharp LH79525 manual available for free PDF download: User Manual

Sharp LH79525 User Manual (555 pages)

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Sharp LH79525 Manuals

Manuals and User Guides for Sharp LH79525. We have 1 Sharp LH79525 manual available for free PDF download: User Manual

Sharp LH79525 User Manual (555 pages)

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