Table 13-43. Usbpre Register; Table 13-44. Usbpre Fields; Table 13-45. Usbpre Register Values; Usb Clock Prescaler Register (Usbpre) - Sharp LH79524 User Manual

Reset, Clock, and Power Controller

13.2.2.18 USB Clock Prescaler Register (USBPRE)

The value in this register is used as a divisor for the clock source to derive the USB clock
(USBCLK) frequency. The USB clock source (PLL clock, or HCLK) is selected with the
PCLKSEL1:USB bit (see Section 13.2.2.13). It is important to note that this bit defaults to
select HCLK, and must be reprogrammed to use the USB PLL as the source for most designs.
The on-board USB Device requires a 48 MHz clock for Full Speed (12 Mbp/s) operation.
The reset value of USBDIV is 0x00, resulting in division by 1. If the USB PLL is pro-
grammed for higher-frequency operation to improve jitter, this field must be programmed
to the appropriate divisor following reset (see Section 13.2.2.23).
Table 13-45 shows the valid combinations for USBDIV and the resulting USB clock fre-
quency. All other USBDIV values are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
13-28

Table 13-43. USBPRE Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0
RO RO RO RO RO

Table 13-44. USBPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
USB Clock Divisor Program with the clock source divisor for the USB Clock
USBDIV
prescaler (Table 13-45).

Table 13-45. USBPRE Register Values

USBDIV
00000000 (default)
00000001
00000010
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFE2000 + 0x4C
DESCRIPTION
DIVISOR
1
2
4
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
USBDIV
0 0 0 0 0
RW RW RW RW RW
ƒ(ADC)
ƒ(clock source)
ƒ(clock source)/2
ƒ(clock source)/4
17 16
0 0
RO RO
1 0
0 0
RW RW