Table 7-9. Memory System Examples; Data Mask Signals - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

7.4.4 Data Mask Signals

Depending on the external memory system width and the operand size, one or two mem-
ory cycles may be required for operand transfer. The Data Mask signals (DQM[3:0]) select
the data phase for each cycle, as shown in Table 7-9.
• For 32-bit wide memory systems, only one memory cycle is required for any data trans-
fer width, with the DQM bits configured on write cycles to disable bytes unaffected by
the transfer.
• For 16-bit wide memory systems, DQM[1] is used as the memory system upper data
mask (UDQM) and DQM[0] is used as the lower data mask (LDQM).
• For 32-bit transfers in 16-bit wide memory systems, two memory data phases are
required to complete the memory cycles. Half word (16-bit) and byte-width transfers
complete in one data phase.
MEMORY SYSTEM
16M by 16-bit
16M by 32-bit
64M by 16-bit
64M by 32-bit

Table 7-9. Memory System Examples

SIZE DATA BUS
32MB D[15:0]
64MB D[31:0]
128MB D[15:0]
256MB D[31:0]
Version 1.0
External Memory Controller
AHB PHYSICAL
BYTE ENABLES
ADDRESS
A[24:1]
A[25:2]
A[26:1]
A[27:2]
DQM[1:0]
DQM[3:0]
DQM[1:0]
DQM[3:0]
7-27