Table 13-22. Pclkctrl0 Register; Table 13-23. Pclkctrl0 Fields; Peripheral Clock Control Register 0 (Pclkctrl0) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0)

This register controls the RTC, UART0, UART1, and UART2 peripheral clocks. Program-
ming a bit to 1 disables the corresponding peripheral's clock. These clocks are more fully
described in Table 13-1.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:10
9
8:3
2
1
0

Table 13-22. PCLKCTRL0 Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO

Table 13-23. PCLKCTRL0 Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
RTC Clock
RTC
1 = Disables the RTC input clock
0 = Enables the RTC input clock
/// Reserved Reading returns 1. Write the reset value.
UART2 Clock Enables and disables the internal clock to UART2.
U2
1 = Disables the UART2 clock
0 = Enables the UART2 clock
UART1 Clock Enables and disables the internal clock to UART1.
U1
1 = Disables the UART1 clock
0 = Enables the UART1 clock
UART0 Clock Enables and disables the internal clock to UART0.
U0
1 = Disables the UART0 clock
0 = Enables the UART0 clock
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
RTC
0 1 1 1
RO RW RW RW
0xFFFE2000 + 0x24
DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
/// U2
1 1 1 1 1
RW RW RW RW RW
17 16
0 0
RO RO
1 0
U1 U0
1 1
RW RW
13-19