Table 15-4. Ctrl0 Register; Table 15-5. Ctrl0 Register Definitions; Register Descriptions - Sharp LH79524 User Manual

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LH79524/LH79525 User's Guide

15.2.2 Register Descriptions

15.2.2.1 Timer 0 Control Register (CTRL0)
This register allows programming the clock divisor, as well as starting/stopping, and clear-
ing the timer count value.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:5
4:2
1
0

Table 15-4. CTRL0 Register

31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RO
RO
RO
RO
RO

Table 15-5. CTRL0 Register Definitions

Reserved Reading this field returns 0. Write the reset value.
///
Timer 0 Clock Select Specifies the timer clock divisor. The timer must be
stopped (with the CS bit) before programming the divisor.
000 = HCLK/2
001 = HCLK/4
010 = HCLK/8
SEL
011 = HCLK/16
100 = HCLK/32
101 = HCLK/64
110 = HCLK/128
111 = CTCLK
Start/Stop Timer 0 Count Specifies whether Timer 0 count is stopped or start-
ed. This bit must be programmed to 0 before programming the SEL bit. For more
information, see Section 15.1.1.
CS
1 = Starts Timer 0
0 = Stops Timer 0
Timer 0 Count Clear Programming a 1 clears the timer count value. This bit
always reads as 0.
CCL
1 = Clears CNT0 contents to 0x0000
0 = Ignored; no effect
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
///
0
0
0
0
RO
RO
RO
RO
0xFFFC4000 + 0x00
DESCRIPTION
Version 1.0
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
SEL
0
0
0
0
0
RO
RO
RW
RW
RW
Timers
17
16
0
0
RO
RO
1
0
CS
CCL
0
0
RW
RW
15-7

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