Table 13-34. Lcdpre Register; Table 13-35. Lcdpre Fields; Table 13-36. Lcdpre Register Values; Lcd Clock Prescaler Register (Lcdpre) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.15 LCD Clock Prescaler Register (LCDPRE)

The value in this register is used as a divisor for HCLK to derive the LCD Data Clock
(LCDDCLK) frequency. Following reset, the prescaler is programmed to pass the clock
through without division. Table 13-36 shows the valid combinations for LCDDIV and the
resulting LCDDCLK frequency. All other LCDDIV values are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0

Table 13-34. LCDPRE Register

31 30 29 28 27
0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0
RO RO RO RO RO

Table 13-35. LCDPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
LCD Data Clock Divisor Program with the divisor for the LCD Data Clock
LCDDIV
prescaler.

Table 13-36. LCDPRE Register Values

LCDDIV
0b00000000 (default)
0b00000001
0b00000010
0b00000100
0b00001000
0b00010000
0b00100000
0b01000000
0b10000000
Reset, Clock, and Power Controller
26 25 24 23
///
0 0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFE2000 + 0x40
DESCRIPTION
DIVIDER
VALUE
1
2
4
8
16
32
64
128
256
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
LCDDIV
0 0 0 0 0
RW RW RW RW RW
ƒ(LCD)
ƒ(HCLK)
ƒ(HCLK)/2
ƒ(HCLK)/4
ƒ(HCLK)/8
ƒ(HCLK)/16
ƒ(HCLK)/32
ƒ(HCLK)/64
ƒ(HCLK))/128
ƒ(HCLK)/256
17 16
0 0
RO RO
1 0
0 0
RW RW
13-25