Clearing Interrupts - Sharp LH79524 User Manual

Vectored Interrupt Controller

18.1.4 Clearing Interrupts

The general procedure for clearing an interrupts is:
1. The interrupt must be cleared at its source, regardless of whether the interrupt source
is external, internal, or software generated.
2. The interrupt must be cleared within the VIC by writing any value to the VECTADDRx
register. Writing a value of 0 is recommended. This action signals the hardware vector
address and priority logic that it can assert a new interrupt and its associated address.
18.1.5 Priority
The VIC can assert an FIQ interrupt and an IRQ interrupt simultaneously. When this
occurs, the CPU gives the FIQ priority over the IRQ interrupt. Priority arbitration for simul-
taneously invoked IRQ interrupts is performed in the VIC hardware.
The priority of IRQ interrupt sources is:
• Vectored interrupts have priority over default-vectored interrupts
• Vectored interrupt priority is from lowest-number to highest-number
• Within the VIC, all default-vectored interrupts have the same priority, which is the
lowest priority.
18.1.6 External Level-Sensitive Interrupts
When external interrupts are configured as level-sensitive, the ISR must ensure that there
is sufficient time between the external interrupts being cleared and the interrupt at the VIC
being cleared. Otherwise, the source of an external interrupt can still be asserted, causing
the VIC to enter the ISR a second time. Because the VIC samples the line after the clear,
it generates another interrupt to the ARM core if the line is recognized to be still active. To
avoid this situation, clear the source of the interrupt as early as practical in the ISR. Doing
so ensures a maximum delay between clearing the external interrupt and clearing the
interrupt at the VIC.
An interrupt line shared by multiple open-collector devices in a wired-OR configuration with
a pull-up resistor can cause multiple interrupts if there is insufficient delay between the time
that the source of the external interrupt is cleared and the time that the interrupt at the VIC
is cleared. This situation is due to the relatively slow rise time of the interrupt signal when
being pulled to its inactive state by the pull-up resistor. The larger the resistor and load
capacitance on the interrupt line, the slower the rise time and the greater the delay required.
18.1.7 Software Guidelines
User software that makes changes to the VIC IRQSTATUS, FIQSTATUS, or RAWINTR reg-
isters should not immediately issue a read to these registers. Instead, at least one Idle cycle
must separate the write and read operations. The Idle cycle(s) is necessary because the VIC
is a zero-wait-state peripheral that requires two clocks for the write operation to update inter-
nal registers. The pipelining of the AHB, along with the VIC not inserting wait states, means
that a read access immediately following a write returns the previous register values.
18-4 Version 1.0
LH79524/LH79525 User's Guide