Table 19-6. Status Description; Table 19-7. Status Fields; Status Register (Status) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

19.2.2.3 Status Register (STATUS)

This register, described in Table 19-6 and Table 19-7, provides the status of the WDT
interrupts, and allows programming whether a system reset is generated upon the first
timeout, or if an interrupt is generated on the first timeout, followed by a system reset if
that interrupt is not serviced before a second timeout occurs.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BIT NAME
31:8
7
6
5
4
3:0

Table 19-6. STATUS Description

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
///
0 0 0 0 0
RO RO RO RO RO
/// Reserved Reading this field returns 0. Write the reset value.
INT This bit reports the WDT timeout interrupt status:
INT
1 = An interrupt has occurred and has been sent to the VIC
0 = No interrupt has occurred
/// Reserved Reading this bit returns 1. Write the reset value.
/// Reserved Reading this bit returns invalid data. Write the reset value.
Interrupt First This bit reports whether the WDT is programmed to assert an
interrupt or a reset on the first timeout. This bit duplicates the value of CTL:IF.
1 = The first timeout generates an interrupt and restarts the WDT. If this interrupt
IF
is not cleared by software or by a reset, the second timeout generates a
system reset. A reset clears this interrupt.
0 = Each timeout generates a system reset
/// Reserved Reading this field returns 0. Write the reset value.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
INT
0 0 0 0
RO RO RO RO
0xFFFE3000 + 0x08

Table 19-7. STATUS Fields

DESCRIPTION
Version 1.0
Watchdog Timer
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
/// IF
1 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
///
0 0
RO RO
19-7