Dma Mode 1: Out Endpoints - Sharp LH79524 User Manual

Universal Serial Bus Device

17.1.5.3 DMA Mode 1: OUT Endpoints

For operation in DMA Mode 0, these steps describe programming an OUT endpoint:
1. Program the proper interrupt enable bit in the OIE register to 1 to enable that interrupt.
2. Program the INDEX register to the EP number.
3. Then program the OUTCSR2:AUTO_CLR, OUTCSR2:USB_DMA_EN, and
OUTCSR2:DMA_MODE bits to 1. This enables DMA bulk transfers and Mode 1 oper-
ation, plus the automatic OUT_PKT_RDY clearing function.
4. Program the DMA registers with:
– ADDRx: Memory address to store packet
– COUNTx: Maximum size of the data buffer
– CNTLx: Program the DMAEN, DMA_MODE, and INTEN bits to 1, and DIRECTION
When a packet is received by the USB Device, the DMA controller requests bus mastership
and transfers the packet to memory. The USB Device automatically clears the
OUT_PKT_RDY bit in the appropriate OUTCSR1 register. This process continues automat-
ically until the USB Device receives a 'short packet' (one of less than the maximum packet
size for the endpoint), signifying the end of the transfer. This 'short packet' will not be trans-
ferred by the DMA controller. Instead the USB Device asserts an interrupt to the VIC. Soft-
ware can then read the OUTCOUNTx register to see the size of the 'short packet' and either
unload it manually or reprogram the DMA controller in Mode 0 to unload the packet.
The DMA controller ADDRx register automatically increments as the packets are unloaded
so software can compare the current value of ADDRx with the start address of the memory
buffer to determine the size of the transfer. If the size of the transfer exceeds the data
buffer size, the DMA controller will stop unloading the FIFO and interrupt the processor.
17-6
to 0. Program the packet size corresponding to OUTMAXP into bits [14:8].
Version 1.0
LH79524/LH79525 User's Guide