Sharp LH79524 User Manual

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LH79524/LH79525

User's Guide

Version 1.0

Table of Contents

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Summary of Contents for Sharp LH79524

Page 1 LH79524/LH79525 User’s Guide Version 1.0...
Page 2 Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED.
Page 3: Table Of Contents
Table of Contents Preface Conventions and Terms ..................xxxv Unconnected (Floating) Inputs ................ xxxv Multiplexed Pins ....................xxxv Pin Names ...................... xxxvi Peripheral Devices ..................xxxvi Register Addresses ..................xxxvi Register Tables ..................... xxxvii Numeric Values .....................xxxviii Block Diagrams .....................xxxviii What’s in This User’s Guide ..................xl Chapter 1 –...
Page 4 Table of Contents LH79524/LH79252 User’s Guide 1.4.2 Hardware Requirements at Reset ............1-10 1.4.2.1 Floating Inputs .................. 1-10 1.4.2.2 Test Pins................... 1-10 1.4.2.3 Active Pull Ups ................. 1-11 1.5 AHB Bus Master Priority and Arbitration ............1-12 1.6 Memory Interface Architecture ............... 1-12 1.7 Instruction and Data Cache................
Page 5 LH79524/LH79252 User’s Guide Table of Contents Chapter 3 – Boot Controller 3.1 Theory of Operation ..................3-2 3.1.1 Boot Device Determination................ 3-2 3.1.1.1 NAND Flash Operation............... 3-4 3.1.2 Hardware Design Considerations.............. 3-4 3.1.2.1 Active Pullups To Signal Boot Mode ..........3-4 3.1.2.2 NAND Flash Hardware Design............
Page 6 Table of Contents LH79524/LH79252 User’s Guide 4.5.3.3 Clock and Signal Polarity Control Register (TIMING2)..... 4-24 4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE)..4-26 4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) ..4-27 4.5.3.6 Interrupt Enable Register (INTREN)..........4-28 4.5.3.7 CLCDC Control Register (CTRL) .............
Page 7 LH79524/LH79252 User’s Guide Table of Contents Chapter 6 – Ethernet MAC Controller 6.1 Theory of Operation ..................6-2 6.1.1 Operational Overview ................6-3 6.1.1.1 Setup ....................6-4 6.1.1.2 Statistics ..................... 6-4 6.1.1.3 Detailed Descriptions................6-4 6.1.2 Memory Interface ..................6-4 6.1.2.1 FIFO ....................
Page 8 Table of Contents LH79524/LH79252 User’s Guide 6.3.3.3 Single Collision Frames (SINGLECOL)..........6-38 6.3.3.4 Multiple Collision Frames (MULTFRM) ..........6-39 6.3.3.5 Frames Received OK (FRMRXOK)..........6-39 6.3.3.6 Frame Check Sequence Errors (FRCHK) ........6-40 6.3.3.7 Alignment Errors (ALIGNERR) ............6-40 6.3.3.8 Deferred Transmission Frames (DEFTXFRM) ......... 6-41 6.3.3.9 Late Collisions (LATECOL) ..............
Page 9 LH79524/LH79252 User’s Guide Table of Contents 7.2.4.6 Extended Wait Transfers ..............7-17 7.3 Interfacing with NAND Flash ................7-17 7.3.1 Booting Example ..................7-17 7.3.2 General NAND Flash Access ..............7-20 7.3.2.1 Transaction Example................ 7-20 7.3.2.2 16-bit Example Transaction.............. 7-21 7.3.2.3 Address Examples................
Page 10 Table of Contents LH79524/LH79252 User’s Guide 7.5.2.24 Static Memory Read Delay Registers (SWAITRDx)....... 7-56 7.5.2.25 Static Memory Page Mode Read Delay Registers (SWAITPAGEx) ..................7-57 7.5.2.26 Static Memory Write Delay Registers (SWAITWRx) ...... 7-58 7.5.2.27 Static Memory Turn Around Delay Registers (STURNx)....7-59 Chapter 8 –...
Page 11 LH79524/LH79252 User’s Guide Table of Contents 10.1.7.1 SSP Protocol Error Interrupt............10-11 10.1.7.2 External Codec Protocol Error Interrupt ........10-11 10.1.7.3 Transmit FIFO Underrun Interrupt ..........10-11 10.1.7.4 Receive Interrupt ................10-12 10.1.7.5 Transmit Interrupt ................. 10-12 10.1.7.6 Receive Overrun Interrupt ............10-12 10.1.7.7 Receive Timeout Interrupt ............
Page 12 Table of Contents LH79524/LH79252 User’s Guide 11.2.2.26 Multiplexing Control 20 Register (MUXCTL20) ......11-38 11.2.2.27 Resistor Configuration Control 20 Register (RESCTL20) ..11-40 11.2.2.28 Multiplexing Control 21 Register (MUXCTL21) ......11-42 11.2.2.29 Resistor Configuration Control 21 Register (RESCTL21) ..11-43 11.2.2.30 Multiplexing Control 22 Register (MUXCTL22) ......
Page 13 LH79524/LH79252 User’s Guide Table of Contents 13.2.2.4 Software Reset Register (SOFTRESET)........13-14 13.2.2.5 Reset Status Register (RSTSTATUS).......... 13-15 13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR) ......13-16 13.2.2.7 System Clock Prescaler Register (SYSCLKPRE) ......13-17 13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE) ......13-18 13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0) .....
Page 14 Table of Contents LH79524/LH79252 User’s Guide Chapter 15 – Timers 15.1 Theory of Operation ..................15-2 15.1.1 Counter Clear Upon Compare Match ............ 15-3 15.1.2 Capture Signal Sampling............... 15-4 15.1.3 PWM Mode.................... 15-4 15.1.3.1 Timer Interrupts ................15-5 15.2 Register Reference ..................15-6 15.2.1 Memory Map ..................
Page 15 LH79524/LH79252 User’s Guide Table of Contents 16.3.2.3 Flag Register (UARTFR) .............. 16-11 16.3.2.4 IrDA Low-Power Counter Register (UARTILPR) ......16-12 16.3.2.5 Integer Baud Rate Divisor Register (UARTIBRD) ......16-13 16.3.2.6 Fractional Baud Rate Divisor Register (UARTFBRD) ....16-14 16.3.2.7 Line Control Register (UARTLCR_H)........... 16-15 16.3.2.8 UART Control Register (UARTCR) ..........
Page 16 Table of Contents LH79524/LH79252 User’s Guide 17.2.3.6 OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP) ... 17-26 17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1) .. 17-27 17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2) ... 17-29 17.2.3.9 Count 0 Register (OUTCOUNT0)..........
Page 17 Figure 3-2. Active Pullup Circuit ................. 3-5 Chapter 4 – Color Liquid Crystal Display Controller Figure 4-1. LH79524/LH79525 LCD System, Simplified Block Diagram....4-1 Figure 4-2. Block Diagram of a Typical Advanced LCD Panel........4-2 Figure 4-3. Color LCD Controller Block Diagram ............4-4 Figure 4-4.
Page 18 List of Figures LH79524/LH79252 User’s Guide Chapter 7 – External Memory Controller Figure 7-1. External Memory Controller Block Diagram..........7-2 Figure 7-2. Automatic Address Shifting..............7-4 Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices ......7-6 Figure 7-4. 16-bit Memory Bank Constructed From 8-bit Devices ......7-6 Figure 7-5.
Page 19 LH79524/LH79252 User’s Guide List of Figures Chapter 14 – Synchronous Serial Port Figure 14-1. SSP Timing Waveform Parameters ............. 14-3 Figure 14-2. Motorola SPI Frame Format (Continuous Transfer) ......14-4 Figure 14-3. Motorola SPI Frame Format with SPH = 0 .......... 14-4 Figure 14-4.
Page 20 Table 1. Register Name ..................xxxvii Table 2. Bit Fields....................xxxvii Chapter 1 – Overview Table 1-1. LH79524/LH79525 Differences..............1-1 Table 1-2. Clock Descriptions ..................1-4 Table 1-3. Port C Settings For Boot ................1-8 Table 1-4. Default Bus Master Priority ..............1-12 Table 1-5.
Page 21 Table 4-5. Palette Data Storage (LH79524 with 16-Bit CLCDC)........ 4-8 Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels ....... 4-10 Table 4-7. Supported Color STN LCD Panels (LH79524 only) ........ 4-10 Table 4-8. Supported Mono-STN LCD Panels ............4-10 Table 4-9.
Page 22 Table 4-39. PALETTE Fields (LH79525 with 12-Bit CLCDC) ........4-36 Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)....... 4-37 Table 4-41. PALETTE Fields (LH79524 with 16-Bit CLCDC) ........4-37 Table 4-42. ALI Register Summary ................4-38 Table 4-43. ALISETUP Register ................4-38 Table 4-44.
Page 23 List of Tables LH79524/LH79252 User’s Guide Table 5-22. CURSLO Fields..................5-12 Table 5-23. CURDHI Register.................. 5-13 Table 5-24. CURDHI Fields..................5-13 Table 5-25. CURDLO Register................. 5-13 Table 5-26. CURDLO Fields ..................5-13 Table 5-27. TCNT Register ..................5-14 Table 5-28. TCNT Fields ..................5-14 Table 5-29.
Page 24 LH79524/LH79252 User’s Guide Table 6-34. PAUSEFRRX Register................6-37 Table 6-35. PAUSEFRRX Fields................6-37 Table 6-36. FRMTXOK Register ................6-38 Table 6-37. FRMTXOK Fields .................. 6-38 Table 6-38. SINGLECOL Register ................6-38 Table 6-39. SINGLECOL Fields ................6-38 Table 6-40. MULTFRM Register ................6-39 Table 6-41.
Page 25 List of Tables LH79524/LH79252 User’s Guide Table 6-81. SPECAD1BOT Fields ................6-50 Table 6-82. SPECAD1TOP Register................ 6-50 Table 6-83. SPECAD1TOP Fields ................6-50 Table 6-84. SPECAD2BOT Register................ 6-51 Table 6-85. SPECAD2BOT Fields ................6-51 Table 6-86. SPECAD2TOP Register................ 6-51 Table 6-87. SPECAD2TOP Fields ................6-51 Table 6-88.
Page 26 Table 7-65. STURNx Fields ..................7-59 Chapter 8 – General Purpose Input/Output Table 8-1. GPIO Ports....................8-1 Table 8-2. LH79524 GPIO Multiplexing..............8-2 Table 8-3. LH79525 GPIO Multiplexing..............8-5 Table 8-4. GPIO Port Memory Map................8-7 Table 8-5. P1DRx Register ..................8-8 Table 8-6.
Page 27 List of Tables LH79524/LH79252 User’s Guide Chapter 9 – I C Module Table 9-1. I C Clock Parameters ................9-3 Table 9-2. Sample I C HIGH Period Counts .............. 9-3 Table 9-3. I C Register Summary ................9-6 Table 9-4. ICCON Register ..................9-7 Table 9-5.
Page 28 LH79524/LH79252 User’s Guide Table 11-13. RESCTL4 Fields ................. 11-8 Table 11-14. MUXCTL5 Register ................11-9 Table 11-15. MUXCTL5 Fields................. 11-9 Table 11-16. RESCTL5 Register................11-10 Table 11-17. RESCTL5 Fields ................11-10 Table 11-18. MUXCTL6 Register ................11-12 Table 11-19. MUXCTL6 Fields................11-12 Table 11-20.
Page 29 Table 12-17. ICR Fields ................... 12-7 Chapter 13 – Reset, Clock, and Power Controller Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies......13-5 Table 13-2. Clock and Enable States for Different Power Modes ......13-6 Table 13-3. RCPC Register Summary ..............13-8 Table 13-4.
Page 30 LH79524/LH79252 User’s Guide Table 13-14. RSTSTATUSCLR Register ............... 13-16 Table 13-15. RSTSTATUSCLR Fields ..............13-16 Table 13-16. SYSCLKPRE Register ..............13-17 Table 13-17. SYSCLKPRE Fields ................13-17 Table 13-18. SYSCLKPRE Register Values ............13-17 Table 13-19. CPUCLKPRE Register..............13-18 Table 13-20. CPUCLKPRE Fields................13-18 Table 13-21.
Page 31 List of Tables LH79524/LH79252 User’s Guide Chapter 14 – Synchronous Serial Port Table 14-1. Feature Comparison ................14-2 Table 14-2. SSP Register Summary ................ 14-9 Table 14-3. CTRL0 Register .................. 14-10 Table 14-4. CTRL0 Fields ..................14-10 Table 14-5. CTRL1 Register .................. 14-12 Table 14-6.
Page 32 LH79524/LH79252 User’s Guide Table 15-24. CNT1 Register .................. 15-19 Table 15-25. CNT1 Register Definitions..............15-19 Table 15-26. T1CMPn Registers................15-20 Table 15-27. T1CMPn Register Definitions............15-20 Table 15-28. T1CAPn Register ................15-21 Table 15-29. T1CAPn Register Definitions ............15-21 Table 15-30. CTRL2 Register ................15-22 Table 15-31.
Page 33 List of Tables LH79524/LH79252 User’s Guide Table 16-29. UARTRIS Fields................16-22 Table 16-30. UARTMIS Register................16-24 Table 16-31. UARTMIS Fields ................16-24 Table 16-32. UARTICR Register................16-26 Table 16-33. UARTICR Fields................16-26 Table 16-34. DMACTRL Register ................16-27 Table 16-35. DMACTRL Fields ................16-27 Chapter 17 –...
Page 34 LH79524/LH79252 User’s Guide Table 17-40. OUTCOUNT0 Register ..............17-30 Table 17-41. OUTCOUNT0 Fields ................. 17-30 Table 17-42. OUTCOUNT1 Register ..............17-30 Table 17-43. OUTCOUNT1 Fields ................. 17-30 Table 17-44. OUTCOUNT2 Register ..............17-31 Table 17-45. OUTCOUNT2 Fields ................. 17-31 Table 17-46. FIFO Register..................17-31 Table 17-47.
Page 35 List of Tables LH79524/LH79252 User’s Guide Chapter 19 – Watchdog Timer Table 19-1. Watchdog Timer Memory Map.............. 19-4 Table 19-2. CTL Register ..................19-5 Table 19-3. CTL Fields..................... 19-5 Table 19-4. RST Description ..................19-6 Table 19-5. RST Field ....................19-6 Table 19-6.
Page 36: Preface
(logical 1 at reset) or pull down (logical 0 at reset) resistors. Multiplexed Pins The LH79524 is manufactured in a CABGA package with 208 pins. The LH79525 is man- ufactured in a LQFP package with 176 pins. Some pins have only one function, but others are multiplexed and may carry as many as three functions.
Page 37: Pin Names
Peripheral Devices The LH79524/LH79525 is an SoC built using the ARM720T RISC core as a base. Objects within the chip but external to the core processor and its support devices are referred to throughout this User’s Guide as ‘blocks’...
Page 38: Register Tables
LH79524/LH79525 User’s Guide Preface Register Tables All Registers are presented in tabular format. A primary table presents each register’s name, address, permissions, bit-field names and the register’s contents at reset. Subse- quent tables detail the specific names and function(s) of all bit fields in the register and explain any important variations that may exist.
Page 39: Numeric Values
Preface LH79524/LH79525 User’s Guide Numeric Values Binary values are prefixed with 0b; for example, 0b00001000. Hexadecimal values are expressed with UPPERCASE letters and prefixed with 0x; for example, 0x0FBC. All numeric values not specifically identified with the above prefixes as either binary or hexadecimal are decimal values.
Page 40: Figure 2. Register With Bit-Field Named
LH79524/LH79525 User’s Guide Preface Block diagrams can include symbols representing Registers and the bit fields within them. Figure 2 shows that the BITFIELDNAME bit field in the REGISTERNAME register enables or disables the signal named OUTPUT. REGISTERNAME:BITFIELDNAME INPUT f ( )
Page 41: What's In This User's Guide
What’s in This User’s Guide Chapter 1 – Overview This Chapter lists the features of the LH79524/LH79525 SoC and presents a simplified block diagram of the device, with the major architectural features identified. Also presented is an overview of the ARM720T processor and MMU. The theory of operation covers bus architecture, bus arbitration, and the base addresses for each of the Advanced High-Per- formance Bus (AHB) and Advanced Peripheral Bus (APB) devices and the APB Bridge.
Page 42: Chapter 7 - External Memory Controller
Chapter 11 – I/O Configuration This Chapter is an overview of the LH79524/LH79525 I/O Configuration and pin multiplex- ing. The Chapter provides a block diagram, programmer’s model, register summary and descriptions.
Page 43: Chapter 15 - Timers
Preface LH79524/LH79525 User’s Guide Chapter 15 – Timers This Chapter describes the LH79524/LH79525 Timers. The Chapter includes a short over- view and block diagram, signal descriptions, operation sequences, register summaries, register descriptions, and interface signals. Chapter 16 – UARTs This Chapter presents the LH79524/LH79525 UART blocks. The Chapter includes a brief overview, block diagram, programmer’s model, programmable parameters, register sum-...
Page 44: Chapter 1 - Overview
Counters/Timers, Real Time Clock, Watchdog Timer, Pulse Width Modulators, and an on-chip Phase-Locked Loop. JTAG support is provided to simplify debugging. Table 1-1 summarizes the differences in features between the LH79524 and the LH79525. All other peripherals and functional blocks are identical (unless noted in the Chapter detail- ing that block’s function).
Page 45: Figure 1-1. Lh79524/Lh79525 Block Diagram
BUS BRIDGE DEVICE 16550 COLOR UART (3) w/SIR TEST SUPPORT CONTROLLER 10 CHANNEL 10-BIT ADC LINEAR ADVANCED (WITH TSC and REGULATOR BROWNOUT INTERFACE DETECTOR) ADVANCED ADVANCED HIGH PERPHERAL PERFORMANCE BUS (APB) BUS (AHB) LH79525-1 Figure 1-1. LH79524/LH79525 Block Diagram Version 1.0...
Page 46: 1.1 Bus Architecture
Overview 1.1 Bus Architecture The LH79524 and LH79525 both internally employ the ARM Advanced Microprocessor Bus Architecture (AMBA) 2.0 bus and bus protocol. They have four Bus Masters on the Advanced High-performance Bus (AHB) that control access to the external memory and the on-chip peripherals.
Page 47: 1.3 Clock Strategy
Overview LH79524/LH79525 User’s Guide 1.3 Clock Strategy The SoCs have two crystal oscillators. One oscillator, CLK OSC, is used to drive both PLLs and the three UARTs, among others. This oscillator supports a frequency range from 10 to 20 MHz. The second oscillator, RTC CLK, is a 32.768 kHz oscillator, also requiring a 1.8 V source.
Page 48 LH79524/LH79525 User’s Guide Overview Table 1-2. Clock Descriptions (Cont’d) FREQUENCY NAME DESCRIPTION (MAX.) This clock controls the data rate for pixel transfers to an external LCD panel. This clock can be separately enabled, disabled and prescaled. CLCD Clock 50.803 MHz (n ≤...
Page 49: 1.3.1 Bus Clocking Modes
Overview LH79524/LH79525 User’s Guide 1.3.1 Bus Clocking Modes The ARM720T core (including the cache) and its AHB interface can be operated using either the Fastbus operation mode or one of two Standard clocking modes (Synchronous or Asynchronous). The clocking modes can have significant impact on power consumption and system throughput, depending upon the application and the speed of external memory.
Page 50: 1.3.1.2 Synchronous And Asynchronous Bus Clocking Modes
LH79524/LH79525 User’s Guide Overview 1.3.1.2 Synchronous and Asynchronous Bus Clocking Modes Although the frequency of FCLK must always be greater than (or equal to) HCLK, the two Standard modes vary the relationship between these two clock signals. In the Synchro- nous Mode, the FCLK frequency must be programmed to be an even integer multiple of the HCLK frequency.
Page 51: 1.4 Reset Strategy
If nTRST is asserted, only the JTAG circuitry is set to its default state. There are two types of internal resets for the LH79524/LH79525. A software reset resets all internal registers, except the JTAG circuitry, to their default state. The other internal reset is the watchdog timer (WDT) reset, which also resets all internal registers, except the JTAG circuitry, to their default state.
Page 52: 1.4.1 Resetting The Test Access Port Controller
LH79524/LH79525 User’s Guide Overview 1.4.1 Resetting the Test Access Port Controller The on-chip Test Access Port (TAP) Controller has an independent reset pin, nTRST. However, it must also be reset at power on, or any time the SoC is reset to ensure it exits the power up sequence in Normal Mode.
Page 53: Figure 1-5. Reset Circuit For Tap Controller Including A Push Button
Overview LH79524/LH79525 User’s Guide SYSTEM RESET TO nRESETIN OTHER PERIPHERALS nRESETIN PUSHBUTTON RESET LH79524/LH79525 POWER ON RESET nTRST nTRST LH79525-118 Figure 1-5. Reset Circuit for TAP Controller Including a Push Button 1.4.2 Hardware Requirements at Reset A number of pins contain on-chip pull up or pull down resistors that provide a logic state following reset.
Page 54: Figure 1-6. Active Pullup Circuit
LH79524/LH79525 User’s Guide Overview 1.4.2.3 Active Pull Ups The boot mode — NOR Flash, NAND Flash, SRAM, I2C, or UART — is selected by the value latched on the rising edge of the nRESETOUT signal from the state of Port C, pins [7:4].
Page 55: Table 1-4. Default Bus Master Priority
• A static and dynamic memory controller with a 24-bit address and 16/32-bit data interface • A 4-channel general purpose DMA controller All system resources accessible by the LH79524/LH79525 are memory mapped. These include external resources (e.g. ROM, PROM, SRAM, SDRAM, External Peripherals) and internal resources (system configuration registers, peripheral configuration registers, and internal memory).
Page 56: Chapter 1 - Overview
LH79524/LH79525 User’s Guide Overview This memory map partition has four configurations, based on the setting of the REMAP bits in the Reset, Clock, and Power Controller. The external static memory bank is divided into four sections, each having a Chip Select associated with it.
Page 57: Table 1-8. Internal Sram Memory Section Mapping
Overview LH79524/LH79525 User’s Guide Table 1-7. SDRAM Memory Section Mapping START ADDRESS DEVICE REMAP = ‘XX’ 0x20000000 - 0x2FFFFFFF Chip Select 0 nDCS0* 0x30000000 - 0x3FFFFFFF Chip Select 1 nDCS1 NOTE: *Also accessible at 0x00000000 when REMAP = 01. Table 1-8. Internal SRAM Memory Section Mapping...
Page 58: Table 1-11. Primary Ahb Peripheral Register Mapping
LH79524/LH79525 User’s Guide Overview Table 1-10. AHB Memory Map on Power-up when Boot Configuration = 0bX1XX ADDRESS REMAP = 00 0x00000000 - 0x1FFFFFFF Boot ROM 0x20000000 - 0x2FFFFFFF SDRAM nDCS0 0x30000000 - 0x3FFFFFFF SDRAM nDCS1 0x40000000 - 0x43FFFFFF Static Memory nCS0...
Page 59: Table 1-12. Apb Peripheral Register Mapping
Overview LH79524/LH79525 User’s Guide Table 1-12. APB Peripheral Register Mapping ADDRESS RANGE DEVICE 0xFFFC0000 - 0xFFFC0FFF UART0 0xFFFC1000 - 0xFFFC1FFF UART1 0xFFFC2000 - 0xFFFC2FFF UART2 0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Convertor 0xFFFC4000 - 0xFFFC4FFF Timer Module 0xFFFC5000 - 0xFFFC5FFF 0xFFFC6000 - 0xFFFC6FFF...
Page 60: Instruction And Data Cache
1.8 Memory Management Unit (MMU) The ARM720T core in the LH79524/LH79525 includes an MMU that performs three pri- mary functions: It translates virtual addresses into physical addresses, it enables cache and write buffering for particular ranges of virtual addresses, and it controls memory access permissions.
Page 61: Theory Of Operation
Chapter 2 Analog-to-Digital Converter/ Brownout Detector The LH79524/LH79525 incorporate an analog-to-digital converter (ADC) and implements a touch screen controller (TSC) and brownout detector with interrupt. 2.1 Theory of Operation The ADC and TSC incorporate: • 10-bit ADC with integrated sample and hold, and fully-differential high impedance signals, and single-ended or ratiometric reference inputs •...
Page 62: Figure 2-1. Adc Block Diagram
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide BrownOut_INTR VREF AN0/UL/X+ AN8/VREF+EXT AN1/UR/X- AN0/UL/X+ A2DCLK_ANALOG AN2/IL/Y+ BANDGAPON 4-TO-1 LL/Y+ AN3/LR/Y- VREF+ ANALOG AN4/WIPER BIAS AND +REF 11-TO-1 CONTROL VREF+ EN D[9:0] AN6/VBAT 10b A/D OUT BGAP VREF START -REF VREF- A2D0N VREF-...
Page 63: Bias-And-Control Network
This configuration also requires a single external MOSFET. • Details for wiring 4-, 5-, 7, and 8-wire touch panels appear in the application note ‘Using the SHARP ADC with Resistive Touch Screens’, available at www.sharpsma.com. Version 1.0...
Page 64: Figure 2-2. Bias-And-Control Network Block Diagram
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide AVDD 100K AVDD PENIRQ AVDD AVDD 11-TO-1 AVDD ANALOG A/D IN+ 100K PENIRQ LH79525-53 Figure 2-2. Bias-and-Control Network Block Diagram Version 1.0...
Page 65: Figure 2-3. Simplified N-Bit Sar Architecture
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.1.3 Clock Generator The ADC has a programmable measurement clock derived from the ADC peripheral clock generated by the RCPC. The clock source is selectable from HCLK or the System oscilla- tor clock, and can be prescaled. The clock supplies the time base for the measurement sequencer and the successive-approximation circuitry.
Page 66: Figure 2-4. Example Of A 4-Bit Sar Adc Operation
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide The analog input voltage (VIN) is held on a track/hold. The N-bit register is set to midscale (100...0, where the most-significant bit is set to 1) to implement the binary search algo- rithm. This forces the DAC output (VDAC) to be VREF ÷ 2, where VREF is the reference voltage provided to the ADC.
Page 67: Figure 2-5. Use Of The Batcntl Pin
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector Four comparison periods are necessary for a 4-bit ADC. Generally, an N-bit SAR ADC requires N comparison periods and will not be ready for the next conversion until the current conversion is completed. Another feature of SAR ADCs is that power dissipation scales with the sample rate. By comparison, flash or pipelined ADCs usually have constant power dissipation as opposed to sample rate.
Page 68: Timing Formulas
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.1.7 Timing Formulas The throughput-conversion time consists of one cycle of Get Data state added to 16 cycles of measurement. Starting from the Idle state, the time for a complete measurement sequence, in clock cycles, is calculated as: 1CIS + MS ×...
Page 69: Pen Interrupt
16 entries. The interrupt is cleared when the FIFO is read. 2.1.9 Application Details An application note entitled ‘Using the SHARP ADC with Resistive Touch Screens’ is avail- able from SHARP that provides more detailed application information dealing with use and programming of the ADC.
Page 70: Table 2-1. Adc Register Summary
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2 Register Reference This section provides the ADC and Brownout Detector register memory mapping and bit fields. 2.2.1 Memory Map The base address for the ADC is 0xFFFC3000. Table 2-1 Summarizes the ADC registers. Address offsets in the table are from the base address.
Page 71: Table 2-2. Hw Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2 Register Descriptions 2.2.2.1 High Word Register (HW) HW is the High Word Register. This Read Only status register shows the contents of the current conversion’s high word in the control bank. There is a one-to-one correspondence between the contents of the control bank high word and the contents of this register for the current conversion in progress.
Page 72: Chapter 2 - Analog-To-Digital Converter/Brownout Detector
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide Table 2-4. In + Mux Definition BIT6 BIT5 BIT4 BIT3 AN0 (UL/X+) AN1 (UR/X-) AN2 (LL/Y+) AN3 (LR/Y-) AN4 (Wiper) VREF - VREF - VREF - VREF - VREF - VREF - 2-12 Version 1.0...
Page 73: Table 2-5. Lw Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.2 Low Word Register (LW) LW is the Control Bank Low Word Register. This Read Only status register displays the contents of the current conversion’s low word in the control bank. There is a one-to-one correspondence between the contents of the control bank low word and the contents of this register for the current conversion in progress.
Page 74: Table 2-7. Rr Register
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.3 Results Register (RR) RR is the Results register. This register contains the oldest entry of the 16-entry × 16-bit wide result FIFO. Its index in the FIFO’s memory array is contained in the Read Pointer (RDPTR) bit field in the FIFO Status Register (see Section 2.2.2.9).
Page 75: Table 2-9. Im Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.4 Interrupt Mask Register (IM) IM is the Interrupt Mask /Enable register. The active bits used in this register are Read/ Write and enable the interrupts. Software can read the status of the interrupt bits through the IS Register, even if corresponding mask bits are set in this register.
Page 76: Chapter 2 - Analog-To-Digital Converter/Brownout Detector
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.5 Power Configuration Register (PC) In this register, the clock divider bits are programmed to set the system clock frequency for analog operation. Program bits [3:0] to the number of conversions necessary, depending on the conversion. Bit [4] can be used as an enable for external I/O pads. If this bit is set to 1, the Battery Control Logic Pin (BATCNTL) will be a valid output.
Page 77: Table 2-13. Touch Screen Controller Power Modes
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector Table 2-12. PC Fields (Cont’d) NAME DESCRIPTION Touch Screen Controller Power Mode Tis field also affects the of the A2DCLK, Band Gap, and A2D signals (see Table 2-13). 00 = Turns off Power Mode and clock; sets the BROWNOUT field (bit [9]) of the GS Register, indicating that a brownout is detected, even if VDDA_ADC is at the correct voltage.
Page 78: Table 2-14. Gc Register
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.6 General Configuration Register (GC) In this register, the SSM field triggers the state machine to retrieve the data from the Control Bank and store it in the appropriate registers for the ADC. If the SSM bits are set to 0b11 at the end of a sequence, the state machine continues to convert data.
Page 79: Table 2-16. Gs Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.7 General Status Register (GS) GS is the General Status Register. In this Read Only register, the 4-bit signal CBSTATE field shows the current state of the Control Bank state machine. The CBTAG signal con- tains the control bank entry number of the conversion that is taking place.
Page 80: Table 2-18. Is Register
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.8 Interrupt Status Register (IS) IS is the Interrupt Status register. This Read Only register provides the unmasked value of each interrupt. The BROWNOUT, PENSYNC, and EOS interrupts are latched and must be cleared by writing to the Interrupt Clear (IC) register. The FWATER and FOVRN inter- rupts are cleared when the contents of the FIFO no longer exceed their thresholds.
Page 81: Table 2-20. Fs Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.9 FIFO Status Register (FS) FS is the FIFO Status Register. This Read Only register indicates the FIFO fill status. Table 2-20. FS Register FIELD RESET FIELD WRPTR RDPTR RESET ADDR 0xFFFC3000 + 0x20 Table 2-21.
Page 82: Table 2-22. Sample Entries For Control Bank
Each entry is a 16-bit register, with its own address space. Table 2-22 shows sample entries for the Control Bank. More details, and examples can be found in SHARP’s Application Note ‘Using the Sharp ADC with Resistive Touch Screens’, available at http://www.sharpsma.com.
Page 83: Table 2-23. Ihwctrl Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.11 Idle High Word Register (IHWCTRL) IHWCTRL is the high word of the Idle Register. The active bits used in this register are Read/Write. This register specifies the idle setting time and the inputs connected to the ADC during the Idle state.
Page 84: Table 2-25. Ilwctrl Register
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.12 Idle Low Word Register (ILWCTRL) ILWCTRL is the low word of the Idle Register. The active bits used in this register are Read/Write. This register specifies the inputs connected to the ADC during the Idle state. This register is used with the IHWCTRL Register (see Section 2.2.2.11).
Page 85: Table 2-27. Mis Register
LH79524/LH79525 User’s Guide Analog-to-Digital Converter/Brownout Detector 2.2.2.13 Masked Interrupt Status Register (MIS) MIS is the Masked Interrupt Status register. This Read Only register gives the masked value of each interrupt. The BROWNOUT, PENSYNC, and EOS interrupts are latched and must be cleared by writing to the Interrupt Clear (IC) register. The FWATER and FOVRN interrupts are cleared when the contents of the FIFO no longer exceed their thresholds.
Page 86: Table 2-29. Ic Register
Analog-to-Digital Converter/Brownout Detector LH79524/LH79525 User’s Guide 2.2.2.14 Interrupt Clear Register (IC) IC is the Interrupt Clear Register. Bits [2:0] of this Write Only register correspond to the three latched interrupts.Writing a 1 to a bit clears the corresponding interrupt; writing a 0 to a bit has no effect.
Page 87: Figure 3-1. Boot Controller Block Diagram
Chapter 3 Boot Controller The Boot Controller is the same for both the LH79524 and LH79525. All references in this chapter apply to both devices. The Boot Controller provides a glueless interface to external NAND Flash devices and support for memory-mapped peripherals or NAND flash devices when performing AHB burst read accesses of undetermined length.
Page 88: Chapter 3 - Boot Controller
Boot Controller LH79524/LH79525 User’s Guide 3.1 Theory of Operation The Boot Controller is a slave module that connects to the APB. It provides hardware sup- port for configuring the External Memory Controller (EMC) interface on power-up, and allows multiple boot devices and scenarios to be used in different applications. The Boot Controller employs no error checking other than that specified by a protocol, if applicable, and does not utilize the MMU or caches.
Page 89: Table 3-1. Boot Configuration For Silicon Version A.0
LH79524/LH79525 User’s Guide Boot Controller Table 3-1. Boot Configuration for Silicon Version A.0 PC[7:4] DEVICE TYPE DATA BUS WIDTH CONTROL NOR Flash or SRAM 16-bit nBLEx LOW for Reads NOR Flash or SRAM 16-bit nBLEx HIGH for Reads NOR Flash or SRAM...
Page 90: Nand Flash Operation
External Memory Controller's nOE, enabled by the signal on external address pin A23. Note that the LH79524/LH79525 memory controller automatically indexes address signals on the address pins, depending on the width of the memory devices. For example, with 8-bit addressing, the A0 signal is presented on pin A0, and the A23 signal is presented on pin A23.
Page 91: Figure 3-2. Active Pullup Circuit
LH79524/LH79525 User’s Guide Boot Controller +3.3 V 120 Ω LH79524/LH79525 BSS84 nRESETOUT BSS84 LH79525-104 Figure 3-2. Active Pullup Circuit 3.1.2.2 NAND Flash Hardware Design The additional NAND Flash control signals are multiplexed with Address lines. Table 3-3 shows the alternate pin functions when using NAND Flash devices.
Page 92: Table 3-5. Supported Devices
LH79524/LH79525 User’s Guide 3.1.2.2.1 NAND Flash Chip Select Because of the hardware implementation of the NAND Flash signalling, the LH79524/ LH79525 chip select used for NAND Flash addressing must be nCS0 for booting; nCS1 cannot be used. Connect the nCS0 pin to the NAND Flash nCE input pin if that device is used for booting.
Page 93: Table 3-6. Uart0 Boot Parameters
LH79524/LH79525 User’s Guide Boot Controller 3.1.4 Booting from UART Another boot option is to boot using UART0. The transfer protocol implementation is XMODEM with 128-byte packets. All UART0 parameters are summarized in Table 3-6. The Boot Controller automatically handles initialization and setup of UART0; the source of the boot code must be compatible with the parameters in the table.
Page 94: Table 3-8. Pbc Register
Boot Controller LH79524/LH79525 User’s Guide 3.2.2 Register Definitions 3.2.2.1 Power-up Boot Configuration Register (PBC) Reading from the PBC register returns the value that the PC[7:4] pins were driven during a power-on reset. This value is used by software contained in the Boot ROM, as well as the Boot Controller, to determine the type and configuration of the external device from which the CPU is to boot.
Page 95: Table 3-10. Cs1Ov Register
LH79524/LH79525 User’s Guide Boot Controller 3.2.3 nCS1 Override Register (CS1OV) Bit 0 in the CS1OV register programs the function of the nCS1 signal. This bit has different functions for read and write. Reading returns the nCS1 Override Enable current status.
Page 96: Table 3-12. Epm Register
Boot Controller LH79524/LH79525 User’s Guide 3.2.4 External Peripheral Mapping Register (EPM) This register determines which chip selects will have burst accesses to their address regions converted to a series of non-sequential transfers. The register provides individual selectability for each of nCS0, nCS1, nCS2, and nCS3. At reset, accesses to all four chip select regions have conversion enabled.
Page 97: Figure 4-1. Lh79524/Lh79525 Lcd System, Simplified Block Diagram
The ALI-specific description begins in Section 4.4. The only difference between the LH79524 CLCDC and the LH79525 CLCDC is the pixel bit depth. The LH79524 supports up to 16 bits-per-pixel (bpp) depth, and the LH79525 supports up to 12 bpp.
Page 98: Figure 4-2. Block Diagram Of A Typical Advanced Lcd Panel
Row and Column driver chips directly. The DC-DC conversion is also handled off-panel, by a separate device operating the panel’s high voltage supplies and illuminator. The DC-DC conversion must be handled by a separate device, since the LH79524/LH79525 do not supply this function.
Page 99: Clcdc Features
– Dual-panel monochrome STN panels, with 4-bit and 8-bit bus interface per panel – Single-panel color STN panels, with an 8-bit bus interface (LH79524 only) – Dual-panel color STN panels, with 8-bit bus interface per panel (LH79524 only) • Resolution up to 1024 × 1024 dots per inch (DPI) •...
Page 100: Figure 4-3. Color Lcd Controller Block Diagram
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide Figure 4-3. Color LCD Controller Block Diagram Version 1.0...
Page 101: Supported Displays And Panels
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller In 12 or 16-bit-per-pixel Mode, the CLCDC uses the unpacked data directly to generate the pixel value. In all other bit-per-pixel modes, the CLCDC uses the unpacked data to index its palette RAM; the CLCDC uses the value indexed from the palette to generate the pixel value.
Page 102: Table 4-1. Pixel Display Arrangement
Table 4-2. Frame Buffer Pixel Storage Format [31:16] DMA FIFO OUTPUT BITS p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 NOTES: 1. LH79525 with 12-Bit CLCDC 2. LH79524 with 16-Bit CLCDC Version 1.0...
Page 103: Table 4-3. Frame Buffer Pixel Storage Format [15:0]
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-3. Frame Buffer Pixel Storage Format [15:0] DMA FIFO OUTPUT BITS NOTES: 1. LH79525 with 12-Bit CLCDC 2. LH79524 with 16-Bit CLCDC Version 1.0...
Page 104: Table 4-4. Palette Data Storage (Lh79525 With 12-Bit Clcdc)
Least Significant Green palette data Unused LR[3:0] Least Significant Red palette data Unused NOTE: *Blue and red palette data can be swapped by programming CTRL:BGR. Table 4-5. Palette Data Storage (LH79524 with 16-Bit CLCDC) NAME* DESCRIPTION Intensity 30:26 MB[4:0] Most Significant Blue palette data...
Page 105: Grayscale Algorithm
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.3.6.1 Grayscale Algorithm A patented grayscale algorithm drives the monochrome and color STN panels. • For monochrome displays, the gray-scale algorithm provides 15 gray scales. • For color displays, the 3-color components (red, green, and blue) are grayscaled simul- taneously.
Page 106: Table 4-6. Supported Tft, Hr-Tft, And Ad-Tft Lcd Panels
LSB of the R, G, and B components of a 6:6:6 TFT panel. NOTES: 1. LH79525 with 12-Bit CLCDC 2. LH79524 with 16-Bit CLCDC Table 4-7. Supported Color STN LCD Panels (LH79524 only) COLOR STN SOURCE NOTE (SINGLE AND DUAL PANEL, 8-BIT BUS)
Page 107: Chapter 4 - Color Liquid Crystal Display Controller
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-9 shows the intensity that can be obtained from each of the 16 possible 4-bit pal- ette combinations. Only 15 of the combinations are useful because the values 0b0110 and 0b1000 produce the same result.
Page 108: Table 4-10. Lh79524 Lcd Data Multiplexing
When LCD data is written to a LCD panel, the manner in which the LCD data is multiplexed onto the external data bus varies for STN, TFT, AD-TFT, or HR-TFT panels. Table 4-10 and Table 4-11 show the data multiplexing for each supported panel. Table 4-10. LH79524 LCD Data Multiplexing CABGA CABGA...
Page 109: Table 4-11. Lh79525 Lcd Data Multiplexing
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-11. LH79525 LCD Data Multiplexing STN MONO 4-BIT PIN NO. PIN NAME SINGLE PANEL DUAL PANEL LCDVD11 MUSTN1 MUSTN1 LCDVD10 MUSTN0 MUSTN0 LCDVD9 LCDVD8 LCDVD7 MLSTN3 LCDVD6 MLSTN2 LCDVD5 MLSTN1 LCDVD4...
Page 110: Table 4-12. Usable Minimum Values Affecting Stn Back Porch Width
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.3.8.1.1 STN Horizontal Timing Restrictions The CLCDC’s dedicated DMA system requests new data at the start of each horizontal dis- play line. Time must be allowed for the DMA transfer operation to occur. Time must also be allowed for the data to propagate down the FIFO path within the LCD interface.
Page 111: Figure 4-4. Lcd Panel Power Sequencing
STN panels. In addition the power down sequence must be fol- lowed or LCD life can be degraded. Figure 4-4 is an example of these timing requirements for the SHARP LM057QCTT03 Color STN LCD Panel, and the accompanying timing specifications. Always refer to your specific LCD panel’s Data Sheet to determine the specific turn-on and turn-off require-...
Page 112: Minimizing A Retained Image On The Lcd
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.3.9.1 Minimizing a Retained Image on the LCD While it is very important to follow the power turn-off sequence to ensure longevity of the LCD panel, this sequence alone will not ensure there is no retained image (ghosting) left on the LCD panel after the LCD has been powered down.
Page 113: Figure 4-5. Ali Simplified Block Diagram
The Advanced LCD Interface (ALI) provides the additional processing required to inter- face the LH79524 and LH79525 to AD-TFT, HR-TFT, or any display technology that uses this method of connection. Figure 4-5 shows the ALI between the CLCDC and the LCD output pins.
Page 114: Ali Theory Of Operation
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.4.1 ALI Theory of Operation All ALI Control and Status Registers can be accessed through the APB. One of the regis- ters, the ALI Setup Register, can be programmed to select Bypass Mode or Active Mode.
Page 115: Table 4-13. Clcdc Register Summary
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5 CLCDC Register Reference This section contains the register definitions for the CLCDC. ALI registers are found in the next section. 4.5.1 Enabling the CLCDC Following reset, the CLCDC Data Clock is gated OFF. Prior to using the CLCDC, it must be enabled by turning on the LCD Data Clock in the PCLKCTRL1 register of the Reset, Clock, and Power Controller block (see Section 13.2.2.10).
Page 116: Table 4-14. Timing0 Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3 CLCDC Register Descriptions 4.5.3.1 Horizontal Timing Panel Control Register (TIMING0) The TIMING0 Register controls: • Horizontal Synchronization Pulse Width (HSW) • Horizontal Front Porch (HFP) period • Horizontal Back Porch (HBP) period •...
Page 117 LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.3.1.1 Horizontal Timing Restrictions The LCD DMA requests new data at the start of a horizontal display line. Some time must be allowed for the DMA transfer and for the data to propagate down the FIFO path in the LCD interface.
Page 118: Table 4-16. Timing1 Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.2 Vertical Timing Panel Control Register (TIMING1) The TIMING1 Register controls the: • Number of Lines-Per-Panel (LPP) • Vertical Synchronization Pulse Width (VSW) • Vertical Front Porch (VFP) period • Vertical Back Porch (VBP) period Table 4-16.
Page 119 LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-17. TIMING1 Fields (Cont’d) NAME DESCRIPTION Lines Per Panel LPP specifies the number of active lines (rows of pixels) per panel. The LPP bit field is a 10-bit value allowing between 1 and 1,024 lines.
Page 120: Table 4-18. Timing2 Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.3 Clock and Signal Polarity Control Register (TIMING2) The TIMING2 Register controls the CLCDC timing. Table 4-18. TIMING2 Register FIELD PCD_HI RESET FIELD PCD_LO RESET ADDR 0xFFFF4000 + 0x08 Table 4-19. TIMING2 Fields...
Page 121 LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-19. TIMING2 Fields (Cont’d) NAME DESCRIPTION Invert the Vertical Synchronization Signal IVS selects the polarity of the LCDFP signal. 1 = LCDFP is active LOW 0 = LCDFP is active HIGH AC Bias Signal Frequency ACB sets the frequency of the LCDEN signal.
Page 122: Table 4-20. Upbase Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.4 Upper Panel Frame Buffer Base Address Register (UPBASE) The UPBASE Register is one of two Color LCD DMA Base Address Registers (the other is LPBASE, described in Section 4.5.3.5). Together with LPBASE, this Read/Write regis- ter programs the base address of the frame buffer.
Page 123: Table 4-22. Lpbase Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.3.5 Lower Panel Frame Buffer Base Address Register (LPBASE) The LPBASE Register is one of two Color LCD DMA Base Address Registers (the other is UPBASE, described in Section 4.5.3.4). Together with UPBASE, this Read/Write register programs the base address of the frame buffer.
Page 124: Table 4-24. Intren Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.6 Interrupt Enable Register (INTREN) INTREN is the Interrupt Enable Register. Setting bits within this register enables the corresponding Raw Interrupt Status bit values to be passed to the Raw Interrupt Status Register (see Section 4.5.3.8).
Page 125: Table 4-26. Ctrl Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.3.7 CLCDC Control Register (CTRL) CTRL controls the CLCDC operating mode. All registers should be set up prior to program- ming LCDEN to 1. Note that the operating mode (color/mono, bits-per-pixel, etc.) can only be changed between frames to avoid corruption of the current frame data.
Page 126: Table 4-27. Ctrl Fields
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide Table 4-27. CTRL Fields NAME DESCRIPTION 31:17 Reserved Reading returns 0. Write the reset value. LCD DMA FIFO Watermark Level 1 = Requests data when either of the two DMA FIFOs have eight or more WATERMARK empty locations.
Page 127 LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-27. CTRL Fields (Cont’d) NAME DESCRIPTION Monochrome STN LCD LCD is Monochrome (Black and White) STN. This bit has no effect in TFT mode. 1 = STN LCD is monochrome 0 = STN LCD is color LCD Bits-Per-Pixel For the LH79525, 12 bpp is selected by 0b100.
Page 128: Table 4-28. Status Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.8 Raw Interrupt Status Register (STATUS) STATUS is the Raw Interrupt Status Register. The status of the interrupts without masking applied is contained in this register. Table 4-28. STATUS Register FIELD RESET...
Page 129: Table 4-30. Interrupt Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.3.9 Masked Interrupt Status Register (INTERRUPT) The INTERRUPT Register is a Read Only register. It is a bit-by-bit logical AND of the Raw Interrupt Status Register (see Section 4.5.3.8) and the INTREN Register (see Section 4.5.3.6).
Page 130: Table 4-32. Intclr Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.10 Interrupt Clear Register (INTCLR) Writing a 1 to an active bit in this register causes that interrupt to be cleared. This is a write- only register. Table 4-32. INTCLR Register FIELD...
Page 131: Table 4-34. Upcurr Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.3.11 LCD Upper Panel and Lower Panel Frame Buffer Current Address Register (UPCURR and LPCURR) UPCURR and LPCURR are registers that contain an approximate value of the upper and lower panel data DMA addresses when read. The registers can change at any time and provide a coarse indication of the current LCD DMA memory pointer.
Page 132: Table 4-38. Palette Register (Lh79525 With 12-Bit Clcdc)
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.3.12 256 × 16-bit Color Palette Register (PALETTE) The PALETTE Registers contain 256 palette entries organized as 128 locations of two entries per word. TFT displays use 12 of the palette entry bits. Each word location contains two palette entries.
Page 133: Table 4-40. Palette Register (Lh79524 With 16-Bit Clcdc)
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC) FIELD MB[4:0] MG[4:0] MR[4:0] RESET — — — — FIELD LB[4:0] LG[4:0] LR[4:0] RESET — — — — ADDR 0xFFFF4000 + 0x200 to 0xFFFF4000 + 0x3FC Table 4-41.
Page 134: Table 4-42. Ali Register Summary
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.4 ALI Register Reference The base address for the ALI is: 0xFFFE4000 Locations at offsets 0x010 through 0xFFF are reserved and must not be used during normal operation. 4.5.5 ALI Memory Map Table 4-42.
Page 135: Table 4-45. Alictrl Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.6.2 Control Register (ALICTRL) ALICTRL is the Control Register. It enables and controls output signals. Table 4-45. ALICTRL Register FIELD RESET FIELD RESET ADDR 0xFFFE4000 + 0x004 Table 4-46. ALICTRL Fields BITS...
Page 136: Table 4-47. Alitiming1 Register
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.5.6.3 Timing Delay Register 1 (ALITIMING1) The ALITIMING1 Register is used for various delays values for output signals. All delays are specified in number of LCD clock (LCDDCLK) periods. Table 4-47. ALITIMING1 Register...
Page 137: Table 4-49. Alitiming2 Register
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 4.5.6.4 Timing Delay Register 2 (ALITIMING2) The ALITIMING2 Register is used for various delay values for output signals. All delays are specified in number of LCD clock (LCDDCLK) periods. Table 4-49. ALITIMING2 Register...
Page 138: Stn Horizontal Timing
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide 4.6 Timing Waveforms This section describes typical output waveform diagrams for the CLCDC and the ALI. 4.6.1 STN Horizontal Timing Figure 4-6 shows typical horizontal timing waveforms for STN panels. In this figure, the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce the LCDDCLK output.
Page 139: Figure 4-6. Stn Horizontal Timing Diagram
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Figure 4-6. STN Horizontal Timing Diagram Version 1.0 4-43...
Page 140: Figure 4-7. Stn Vertical Timing Diagram
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide Figure 4-7. STN Vertical Timing Diagram 4-44 Version 1.0...
Page 141: Figure 4-8. Tft Horizontal Timing Diagram
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller Figure 4-8. TFT Horizontal Timing Diagram Version 1.0 4-45...
Page 142: Figure 4-9. Tft Vertical Timing Diagram
Color Liquid Crystal Display Controller LH79524/LH79525 User’s Guide Figure 4-9. TFT Vertical Timing Diagram 4-46 Version 1.0...
Page 143: Figure 4-10. Ad-Tft, Hr-Tft Horizontal Timing Diagram
LH79524/LH79525 User’s Guide Color Liquid Crystal Display Controller 1 AD-TFT or HR-TFT HORIZONTAL LINE CLCDCLK (INTERNAL) APBPERIPHCLKCTRL1:LCD AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED CLKPRESCALE:LCDPS (SHOWN FOR REFERENCE) TIMING0:HSW LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC...
Page 144: Chapter 5 - Direct Memory Access Controller
Chapter 5 Direct Memory Access Controller The DMA Controller in the LH79524/LH79525 is identical in each SoC; all descriptions in this chapter apply to both devices. The DMA Controller provides four concurrent data streams and three modes of transfer: • Memory to Memory (selectable on Stream 3 only) •...
Page 145 Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.1 Theory Of Operation The SoC uses a central DMA Controller to service all DMA requirements for DMA-capable devices. The DMA Controller provides DMA support for the DMA-capable peripherals listed in Table 5-1. The DMA Controller has an APB slave port for programming its registers and an AHB port for data transfers.
Page 146: Use For Ssp And Uart
LH79524/LH79525 User’s Guide Direct Memory Access Controller The DMA process comprises: The external request signal (DREQ) starts a peripheral DMA transfer. The DMA Controller requests use of the AHB. When the AHB arbiter grants the AHB to the DMA Controller, the DMA Controller fills its FIFO with the number of data units specified by the burst length (1, 4, 8, or 16).
Page 147: Figure 5-1. Basic Dma Timing
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.1.3 Interrupt, Error, and Status Registers The DMA Controller provides Interrupt, Error, and Status Registers for controlling the gen- eration of an interrupt, error-handling control, and active-stream monitoring. Each stream has its own interrupt flag, which is set after the last transfer completes. Each of the four interrupt flags can be masked and cleared independently.
Page 148: Table 5-2. Dma Memory Map
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2 Register Reference This section provides the DMA Controller register memory mapping and bit fields. 5.2.1 Memory Map Each stream has the identical set of 11 registers. The base address for each stream is shown in Table 5-2.
Page 149: Chapter 5 - Direct Memory Access Controller
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.2.2 Register Definitions 5.2.2.1 Source Base Registers (SOURCELO and SOURCEHI) The two 16-bit Source Base Registers contain the 32-bit source base address for the next DMA transfer. When the DMA Controller is enabled, the contents of the Source Base Reg- isters load into the Current Source Address Register.
Page 150: Table 5-8. Destlo Register
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2.2.2 Destination Base Registers (DESTLO and DESTHI) The two 16-bit Destination Base Register contain the 32-bit destination base address for the next DMA transfer. When the DMA Controller is enabled, the contents of the Destina- tion Base Address Registers load into the Current Destination Address Register.
Page 151: Table 5-12. Max Register
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.2.2.3 Maximum Count Register (MAX) The Maximum Count Register must be programmed with the maximum number of data units of the next DMA transfer. A data unit equals the source-to-DMA data width (byte, half- word or word).
Page 152: Table 5-14. Ctrl Register
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2.2.4 Control Register (CTRL) The Control Register contains the configuration of the DMA Controller. Constraints on the field values based on the stream type are defined in Table 5-18. Where a value appears in this table, that is the only valid value for that stream, and the field must be programmed to this value.
Page 153: Table 5-16. Dma Data Width
Direct Memory Access Controller LH79524/LH79525 User’s Guide Table 5-15. CTRL Fields (Cont’d) NAME DESCRIPTION Peripheral Burst Size Defines the number of peripheral data units in the peripheral burst. Using the peripheral as the destination, the DMA interface SOBURST automatically reads the correct number of source words to compile a trans- action.
Page 154: Table 5-18. Constraints On Ctrl Field Values Based On Stream Type
LH79524/LH79525 User’s Guide Direct Memory Access Controller Table 5-18. Constraints on CTRL Field Values Based on Stream Type STREAM DESIZE SOBURST SOSIZE DEINC SOINC TYPE SSPRX (Stream 0) All valid values 00 or 10 SSPTX (Stream 1) 00 or 10...
Page 155: Table 5-19. Curshi Register
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.2.2.5 Current Source Registers (CURSHI and CURSLO) The Current Source Registers are 16-bit Read Only registers that hold the current value of the source address pointer. The value in the registers is used as an AHB address in a source-to-DMA data transfer over the AHB.
Page 156: Table 5-23. Curdhi Register
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2.2.6 Current Destination Registers (CURDHI and CURDLO) The Current Destination Registers are 16-bit Read Only registers that hold the current value of the destination address pointer. The value in the registers is used as an AHB address in a DMA-to-destination data transfer over the AHB.
Page 157: Table 5-27. Tcnt Register
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.2.2.7 Terminal Count Register (TCNT) The Terminal Count Register is a 16-bit Read Only register that contains the number of data units remaining in the current DMA transfer. The data unit is equal to the source-to- DMA data width (byte, half-word or word).
Page 158: Table 5-29. Mask Register
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2.2.8 Interrupt Mask Register (MASK) The MASK Register allows enabling and disabling (masking) DMA interrupts. Program with a 1 to enable, and a 0 to disable individual interrupts. Table 5-29. MASK Register FIELD...
Page 159: Table 5-31. Clr Register
Direct Memory Access Controller LH79524/LH79525 User’s Guide 5.2.2.9 Interrupt Clear Register (CLR) The Interrupt Clear Register clears the status flags. Writing a 1 to a bit clears the interrupt status bit in the STATUS register. This register has an indeterminate value after Reset.
Page 160: Table 5-33. Status Register
LH79524/LH79525 User’s Guide Direct Memory Access Controller 5.2.2.10 Status Register (STATUS) The STATUS Register provides status information about the DMA Controller interrupts. The interrupt status bits are cleared by writing to the CLR register. The INT[3:0] bits are the data stream interrupt flags corresponding to data stream 0 through data stream 3.
Page 161 Direct Memory Access Controller LH79524/LH79525 User’s Guide Table 5-34. STATUS Fields (Cont’d) NAME DESCRIPTION Data Stream 3 Error Interrupt Contains the status of the data stream 3 error interrupt. ERRORINT3 1 = Error-interrupt asserted 0 = Error-interrupt not asserted Data Stream 2 Error Interrupt Contains the status of the data stream 2 error interrupt.
Page 162: Chapter 6 - Ethernet Mac Controller
Chapter 6 Ethernet MAC Controller The on-board Ethernet Media Access Controller (EMAC) is compatible with IEEE 802.3, and has passed the University of New Hampshire (UNH) testing. It supports both 10- and 100-Mbit/s transfer rates, and full and half duplex operation. Other features include: •...
Page 163: Figure 6-1. Emac Block Diagram
The EMAC is identical for both the LH79524 and LH79525, and all descriptions in this chapter apply to both devices. Following the Theory of Operation section is a programming example.
Page 164: Operational Overview
The Statistics and Control Registers are accessed by the core via the APB, through the Register Interface. The Statistics Registers log a wide range of network statistics for use by the LH79524/LH79525 software, RMON/MIB, or other uses. The control registers allow software to define network parameters, enable and disable the Receive and Transmit Blocks, enable and disable interrupts, view status information, and also implement the MDIO interface to manage the PHY.
Page 165: Setup
EMAC, buffers, DMA, and specific operation. 6.1.2 Memory Interface Ethernet frame data is stored in LH79524/LH79525 system memory. It is transferred to and from the Ethernet MAC through the DMA interface. All transfers are 32-bit words and may be single accesses, or bursts of 2, 3, or 4 words (transfers for the LH79525 are auto- matically parsed into two 16-bit transfers to accommodate its 16-bit data bus).
Page 166: Table 6-1. Receive Buffer Descriptor List
LH79524/LH79525 User’s Guide Ethernet MAC Controller Each Receive Buffer Descriptor List entry comprises two words. The first word contains only the address of the receive buffer; the second word contains the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the Start Of Frame bit and the offset bits, if appropriate.
Page 167 Ethernet MAC Controller LH79524/LH79525 User’s Guide To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. Bit zero must be written with 0. Bit one is the wrap bit and indicates the last entry in the list.
Page 168: Table 6-2. Transmit Buffer Descriptor List
LH79524/LH79525 User’s Guide Ethernet MAC Controller A Receive Overrun condition occurs when either the AHB bus was not granted in time or because the response was ‘Not OK’. In a Receive Overrun condition, the Receive Overrun Interrupt is asserted and the buffer currently being written is recovered. The next received...
Page 169 Ethernet MAC Controller LH79524/LH79525 User’s Guide Before transmitting frames, the buffer descriptors must be initialized by writing an appro- priate address to bits [31:0] in the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with a CRC, and whether the buffer is the last buffer of the frame.
Page 170: Receive Block
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.1.3 Receive Block The Receive Block checks for a valid preamble, FCS, alignment, and length; presents received frames to the DMA Block; and stores the frame’s destination address for use by the Address Checking Block.
Page 171: Table 6-3. Pause Frame Support
Ethernet MAC Controller LH79524/LH79525 User’s Guide The Back-Off Time is based on an Exclusive OR of the 10 least-significant bits of the data stream from the transmit FIFO and a 10-bit pseudo-random number generator. The num- ber of bits used depends on the number of collisions seen. After the first collision one bit is used, the second two, and so on up to 10.
Page 172: Address Checking Block
LH79524/LH79525 User’s Guide Ethernet MAC Controller If either NETCTL: is programmed to 1, a pause frame TXZEROQ or NETCTL:TXPAUSEFM will be transmitted only if full duplex is selected in the NETCONFIG register, and transmit is enabled in the NETCTL register. Pause frame transmission occurs immediately if trans- mit is inactive or if transmit is active between the current frame and the next frame due to be transmitted.
Page 173: Broadcast Address
Ethernet MAC Controller LH79524/LH79525 User’s Guide The destination address of received frames is compared against the data stored in the specific address registers once they have been programmed. The addresses are deacti- vated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written, preventing a partial address from becoming active.
Page 174: Table 6-4. Vlan Support
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.1.5.4 Type ID Checking The contents of the IDCHK register are compared against the Length/Type ID of received frames. Bit 22 in the Receive Buffer Descriptor List is 1 if there is a match (see Table 6-1).
Page 175: Initialization
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.2.1 Initialization Initialization of the EMAC configuration must be done while the transmit and receive cir- cuits are disabled. See the descriptions of the Network Control register and Network Con- figuration register in Register Reference section.
Page 176: Figure 6-2. Address Matching
LH79524/LH79525 User’s Guide Ethernet MAC Controller HASH ADDRESS REGISTERS DESTINATION ADDRESS (CONTAINED IN INDEX RECEIVED FRAME) MATCH HASH MATCH 1 SPECIFIC ADDRESS 1 MATCH 2 SPECIFIC ADDRESS 2 MATCH 3 SPECIFIC ADDRESS 3 MATCH 4 SPECIFIC ADDRESS 4 LH79525-65 Figure 6-2. Address Matching The RXBQP register points to the next entry in the Receive Buffer Descriptor List and the EMAC uses this as the address in system memory to which the frame is written.
Page 177: Transmit Buffer List
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.2.1.2 Transmit Buffer List Transmit data is read from buffers assigned to system memory. These buffers are described in the Transmit Buffer Queue, which is a sequence of Transmit Buffer Descriptor entries as defined in Table 6-2.
Page 178: Phy Maintenance
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.2.1.5 PHY Maintenance The PHYMAINT register enables the EMAC to communicate with a PHY using the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are con- figured for the same speed and either half- or full-duplex configuration.
Page 179: Table 6-5. Emac Register Summary
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3 Register Reference This section provides the EMAC register memory mapping and bit fields. 6.3.1 Memory Map The base address for the EMAC is 0xFFFC7000. Table 6-5 Summarizes the EMAC registers. There are three types of registers in the EMAC: control, configuration, and status registers;...
Page 180 LH79524/LH79525 User’s Guide Ethernet MAC Controller Table 6-5. EMAC Register Summary (Cont’d) ADDRESS NAME DESCRIPTION OFFSET 0x68 SENSERR Carrier sense errors 0x6C RXRERR Receive resource errors 0x70 RXOVERR Receive overrun errors 0x74 RXSYMERR Receive symbol errors 0x78 LENERR Excessive length errors...
Page 181: Table 6-6. Netctl Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2 Control, Configuration, And Status Register Definitions 6.3.2.1 Network Control Register (NETCTL) The NETCTL register allows configuration and testing of the SoC on the network. Table 6-6. NETCTL Register FIELD RESET TYPE FIELD RESET...
Page 182 LH79524/LH79525 User’s Guide Ethernet MAC Controller Table 6-7. NETCTL Fields (Cont’d) BITS NAME FUNCTION Write Enable for Statistics Registers Makes the statistics registers writable for functional test purposes. WRENSTAT 1 = Make statistics registers writable 0 = No action Increment Statistics Registers Increment all the statistics registers by one for test purposes.
Page 183: Table 6-8. Netconfig Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.2 Network Configuration Register (NETCONFIG) This register allows general network configuration. Table 6-8. NETCONFIG Register FIELD RESET TYPE FIELD RESET TYPE ADDR 0xFFFC7000 + 0x04 Table 6-9. NETCONFIG Fields BITS NAME FUNCTION 31:20 Reserved Reading returns 0. Write the reset value.
Page 184 LH79524/LH79525 User’s Guide Ethernet MAC Controller Table 6-9. NETCONFIG Fields (Cont’d) BITS NAME FUNCTION Retry Test Must be programmed to 0 for normal operation. If programmed to 1, the delay between collisions will always be one slot time. Setting this bit to 1 helps testing the ‘Too Many Entries’...
Page 185: Table 6-10. Netstatus Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.3 Network Status Register (NETSTATUS) The NETSTATUS register is a read-only register that reports status of the PHY and MDIO. Table 6-10. NETSTATUS Register FIELD RESET TYPE FIELD RESET — — TYPE ADDR 0xFFFC7000 + 0x08 Table 6-11.
Page 186: Table 6-12. Txstatus Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.2.4 Transmit Status Register (TXSTATUS) This register provides transmit status details. Individual bits may be cleared by writing 1 to them. It is not possible to program a bit to 1 by writing to the register.
Page 187 Ethernet MAC Controller LH79524/LH79525 User’s Guide Table 6-13. TXSTATUS Fields (Cont’d) BITS NAME FUNCTION Buffers Exhausted Mid-Frame If the buffers run out of data during transmission of a frame, transmission stops. When this happens, FCS is bad and the Transmit Error (ETHERTXER) pin is asserted.
Page 188: Table 6-14. Rxbqp Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.2.5 Receive Buffer Queue Pointer (RXBQP) This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1,024 buffers, or when bit 1 of the entry is set.
Page 189: Table 6-16. Txbqp Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.6 Transmit Buffer Queue Pointer (TXBQP) This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1,024 buffers, or when the wrap bit of the entry is set.
Page 190: Table 6-18. Rxstatus Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.2.7 Receive Status Register (RXSTATUS) Read this register to obtain details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register Table 6-18.
Page 191: Table 6-20. Instatus Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.8 Interrupt Status Register (INSTATUS) The EMAC generates a single interrupt. This register indicates the source of this interrupt. For test purposes each bit can be set or reset by directly writing to the interrupt status reg- ister regardless of the state of the mask register.
Page 192 LH79524/LH79525 User’s Guide Ethernet MAC Controller Table 6-21. INSTATUS Fields (Cont’d) BITS NAME FUNCTION Transmit Complete Denotes a frame has been successfully trans- mitted. This bit is reset to 0 when read. TXCOMPLETE 1 = Transmit complete 0 = No complete transmit Transmit Buffers Exhausted In Mid-frame The transmit buffers have run out of data before the transmission of the frame completed.
Page 193: Table 6-22. Enable Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.9 Interrupt Enable Register (ENABLE) At reset all interrupts are disabled. Writing a 1 to the relevant bit location enables the required interrupt. This register is write only Table 6-22. ENABLE Register FIELD RESET...
Page 194: Table 6-24. Disable Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.2.10 Interrupt Disable Register (DISABLE) This register is used to disable individual interrupts. All interrupts are disabled following a reset. Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only.
Page 195: Table 6-26. Mask Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.11 Interrupt Mask Register (MASK) The MASK register is a read-only register that shows the status of the interrupt based on what has been written to the ENABLE and DISABLE registers. As all interrupts are dis- abled following reset, the interrupt bits in this register are reset to 1.
Page 196: Table 6-28. Phymaint Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.2.12 PHY Maintenance Register (PHYMAINT) This register enables the EMAC to communicate with a PHY by means of the MDIO inter- face. It is used during auto negotiation to ensure that the EMAC and the PHY are config- ured for the same speed and duplex configuration.
Page 197: Table 6-30. Pausetime Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.2.13 Pause Time Register (PAUSETIME) The PAUSETIME register contains the current value of PAUSETIME, which is decre- mented once every 512 bit-times (one slot time). Table 6-30. PAUSETIME Register FIELD RESET TYPE FIELD PAUSETIME...
Page 198: Table 6-34. Pausefrrx Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3 Statistics Register Definitions Statistics registers accumulate statistics for software drivers, RMON applications, and other uses. Reading statistics registers resets the counts to zero. If they are not read before reaching maximum count, the count does not wrap, but sticks at all 1s. The receive statistics registers only increment when the NETCTL:RXEN is programmed to 1.
Page 199: Table 6-36. Frmtxok Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.2 Frames Transmitted OK (FRMTXOK) This is a 24-bit register counting the number of frames successfully transmitted (no under- run and no excessive retry errors). Table 6-36. FRMTXOK Register FIELD FRMTXOK RESET TYPE FIELD...
Page 200: Chapter 6 - Ethernet Mac Controller
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3.4 Multiple Collision Frames (MULTFRM) This register counts the number of frames that experienced between two and 15 collisions before successful transmission. Table 6-40. MULTFRM Register FIELD RESET TYPE FIELD MULTFRM RESET TYPE ADDR 0xFFFC7000 + 0x48 Table 6-41.
Page 201: Table 6-44. Frchk Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.6 Frame Check Sequence Errors (FRCHK) This register hold the count of frames an integral number of bytes-long, have a bad CRC, and are between 64 and 1,518 bytes in length (1,522 if NETCONFIG:RECBYTE is 1).
Page 202: Table 6-48. Deftxfrm Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3.8 Deferred Transmission Frames (DEFTXFRM) This is a 16-bit register containing the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any col- lision are not counted nor are frames that experienced a transmit underrun.
Page 203: Table 6-52. Excol Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.10 Excessive Collisions (EXCOL) This register compiles the number of frames not transmitted due to more than 16 collisions occuring during transmission attempts. Table 6-52. EXCOL Register FIELD RESET TYPE FIELD EXCCOL RESET TYPE...
Page 204: Table 6-56. Senserr Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3.12 Carrier Sense Errors (SENSERR) This register counts the number of Carrier Sense errors. Table 6-56. SENSERR Register FIELD RESET TYPE FIELD SENSERR RESET TYPE ADDR 0xFFFC7000 + 0x68 Table 6-57. SENSERR Fields BITS...
Page 205: Table 6-58. Rxrerr Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.13 Receive Resource Errors (RXRERR) This register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. Table 6-58. RXRERR Register FIELD...
Page 206: Table 6-62. Rxsymerr Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3.15 Receive Symbol Errors (RXSYMERR) This register counts the number of frames that had ETHERRXER asserted during reception. Table 6-62. RXSYMERR Register FIELD RESET TYPE FIELD RXSYMERR RESET TYPE ADDR 0xFFFC7000 + 0x74 Table 6-63. RXSYMERR Fields...
Page 207: Table 6-66. Rxjab Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.17 Receive Jabbers (RXJAB) This is an 8-bit register containing the number of frames received exceeding 1,518 bytes (1,522 if NETCONFIG:RECBYTE is 1) in length and have either a CRC error, an alignment error, or a receive symbol error Table 6-66.
Page 208: Table 6-70. Sqerr Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.3.19 SQE Test Errors (SQERR) This 8-bit register contains the number of frames where the ETHERCOL pin was not asserted within 96 bit times (one inter-frame gap) of the ETHERTXEN pin being deas- serted in half-duplex mode.
Page 209: Table 6-74. Txpausefm Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.3.21 Transmitted Pause Frames (TXPAUSEFM) This register contains the number of Pause Frames transmitted. Table 6-74. TXPAUSEFM Register FIELD RESET TYPE FIELD TXPAUSEFM RESET TYPE ADDR 0xFFFC7000 + 0x8C Table 6-75. TXPAUSEFM Fields BITS...
Page 210: Table 6-76. Hashbot Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.4 Matching Registers The matching registers allow programming specific addresses or Type IDs for matching with incoming frames. 6.3.4.1 Hash Register Bottom (HASHBOT) This register contains the low-order bits of the Hash Address Register (bits [31:0]). For more information, see Section 6.1.5.2 for more information on hash addressing.
Page 211: Table 6-80. Specad1Bot Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.4.3 Specific Address 1 Bottom (SPECAD1BOT) This register contains the least-significant bits (bits [31:0]) of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received .
Page 212: Table 6-84. Specad2Bot Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.4.5 Specific Address 2 Bottom (SPECAD2BOT) This register contains the least-significant bits of the destination address (bits [31:0]). Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
Page 213: Table 6-88. Specad3Bot Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.4.7 Specific Address 3 Bottom (SPECAD3BOT) This register contains the least-significant bits of the destination address (bits [31:0]). Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
Page 214: Table 6-92. Specad4Bot Register
LH79524/LH79525 User’s Guide Ethernet MAC Controller 6.3.4.9 Specific Address 4 Bottom (SPECAD4BOT) This register contains the least-significant bits of the destination address (bits [31:0]). Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received Table 6-92.
Page 215: Table 6-96. Idchk Register
Ethernet MAC Controller LH79524/LH79525 User’s Guide 6.3.4.11 Type ID Checking (IDCHK) This register contains the TypeID/Length to compare to received frames. Table 6-96. IDCHK Register FIELD RESET TYPE FIELD IDCHK RESET TYPE ADDR 0xFFFC7000 + 0xB8 Table 6-97. TypeIDCheck Fields...
Page 216: Chapter 7 - External Memory Controller
• Low transaction latency • Read and Write buffers to reduce latency and to improve performance • 8-bit and 16-bit wide static memory support (32-bit support in the LH79524) • 16-bit wide synchronous SDRAM memory support (32-bit support in the LH79524) •...
Page 217: Figure 7-1. External Memory Controller Block Diagram
External Memory Controller LH79524/LH79525 User’s Guide SDRAM MEMORY CONTROL LOW-POWER SDRAM DATA SYNCHRONOUS BUFFERS INTERFACE FLASH ENDIANIZATION SDRAM PACKING LOGIC TEST INTERFACE CONTROLLER FLASH LH79525-62 Figure 7-1. External Memory Controller Block Diagram The EMC supports six banks of external memory. Together these banks occupy 384MB of address space.
Page 218: External Memory Map
CS10V register, described in Section 3.2.3. 7.2 Static Memory The static memory interface is externally asynchronous. However, the LH79524/LH79525 generates the external asynchronous signals using the internal system clock to synchro- nously control the switching. Thus, the timing of static memory signals is easily referenced to the internal system clock frequency.
Page 219: Figure 7-2. Automatic Address Shifting
External Memory Controller LH79524/LH79525 User’s Guide INTERNAL TO EXTERNAL TO THE LH79524/LH79525 THE LH79524/LH79525 MEMORY WIDTH NOTE: MEMORY WIDTH (SCONFIGx:MW) 00 = 8 BIT 01 = 16 BIT 10 = 32 BIT LH79525-114 Figure 7-2. Automatic Address Shifting Version 1.0...
Page 220: Hardware Design
LH79524/LH79525 User’s Guide External Memory Controller 7.2.2 Hardware Design Automatic address shifting makes hardware design much simpler. This section provides a description and guide for hardware design and interfacing. 7.2.2.1 Address Connectivity Rather than connecting different address pins to different memory devices depending on the width, SoC address pin A0 always connects to device pin A0, SoC address pin A1 to device pin A1, continuing through SoC pin A23 connecting to device pin A23.
Page 221: Figure 7-3. 32-Bit Memory Bank Constructed From 8-Bit Devices
External Memory Controller LH79524/LH79525 User’s Guide A[20:0] A[20:0] A[20:0] A[20:0] A[20:0] nBLE3 nBLE2 nBLE1 nBLE0 D[31:24] IO[7:0] D[23:16] IO[7:0] D[15:8] IO[7:0] D[7:0] IO[7:0] LH79525-82 Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices A[20:0] A[20:0] A[20:0] nBLE1 nBLE0 D[15:8] D[7:0]...
Page 222: Figure 7-6. 32-Bit (Left) And 16-Bit (Right) Memory Banks Constructed From 16-Bit Devices
LH79524/LH79525 User’s Guide External Memory Controller A[20:0] A[20:0] A[20:0] A[20:0] A[20:0] nBLE1 nBLE3 nBLE1 nBLE2 nBLE0 nBLE0 D[31:16] IO[15:0] D[15:0] IO[15:0] D[15:0] IO[15:0] LH79525-85 Figure 7-6. 32-bit (left) and 16-bit (right) Memory Banks Constructed From 16-bit Devices A[20:0] A[20:0] nBLE3...
Page 223: Figure 7-8. Typical Memory Connection Diagram
External Memory Controller LH79524/LH79525 User’s Guide D[31:0] A[20:0] A[20:0] Q[31:0] nCS0 2M × 32 BURST MASK ROM D[31:16] IO[15:0] A[15:0] nCS1 D[15:0] A[15:0] IO[15:0] 64K × 16 SRAM, × 2 D[31:24] A[16:0] IO[7:0] nCS2 nBLE3 D[23:16] A[16:0] IO[7:0] nBLE2 D[15:8]...
Page 224: Figure 7-9. Pre-Shifting Routine
LH79524/LH79525 User’s Guide External Memory Controller 7.2.3 Software Design For the bulk of software designs, the automatic address shifting is completely transparent and no software considerations are needed. However, in instances where software must control the signal on a specific address pin, the design must account for any address shifting.
Page 225: Table 7-1. Static Memory Configurations
‘B’ = SWAITWRx; ‘C’ = the 1 HCLK-cycle address delay; ‘D’ = SWAITOENx; and ‘E’ = SWAITRD. These diagrams are intended solely to illustrate programming effects. Actual timing diagrams and timing tables appear in the LH79524/LH79525 Data Sheet. 7-10 Version 1.0...
Page 226: Figure 7-10. Static Read Transaction With Zero Wait States
LH79524/LH79525 User’s Guide External Memory Controller 7.2.4.1.1 Read Cycle Wait States Figure 7-10 shows the Read cycle with zero wait states. As shown in the Figure, SWAIT- OENx and SWAITRDx (refer to Section 7.5.2.23 and Section 7.5.2.24 for register descrip- tions) are both programmed to zero, for minimum Read Cycle time.
Page 227: Figure 7-11. Static Read Transaction With Three Wait States
External Memory Controller LH79524/LH79525 User’s Guide In Timing B, three wait states are also illustrated. However, in this case, the three wait states have been programmed by setting SWAITRDx to 0x2 and SWAITOENx to 0x1. In this case, nOE does not become asserted at the same time as nCSx. Instead, nOE is delayed by the number of HCLK periods enumerated by SWAITOENx, which in this case is one, represented by time ‘D1’.
Page 228: Figure 7-12. Static Write Transaction With Zero Wait States
LH79524/LH79525 User’s Guide External Memory Controller The total Read cycle time is the time that the address is valid (in the figures, until the end of the ‘C’ time). In general, Read wait states can be derived from the following equation: tRC (Read cycle time) = tD1 + tD2 + ...
Page 229 External Memory Controller LH79524/LH79525 User’s Guide In the Figure, nCSx is asserted coincident (with a small propagation delay) with the address becoming valid (Valid Address in the Figure). Data becomes valid another small propaga- tion delay later. Unlike Read transactions, nWE (or nBLEx) assertion is always delayed one HCLK cycle, time ‘A0’...
Page 230: Figure 7-13. Static Write Transaction With Two Wait States
LH79524/LH79525 User’s Guide External Memory Controller TIMING A HCLK A[23:0] VALID ADDRESS D[31:0] VALID DATA nCSx nWE or nBLEx NOTES: With Register Programming: SWAITWENx = A = 0x0 SWAITWRx = B = 0x2 C = Address hold TIMING B nCSx...
Page 231: Bus Turnaround
The system clock cycle in which the nCSx signal is asserted counts as the first wait state. Timing diagrams and extensive descrip- tions appear the the LH79524/LH79525 Data Sheet. 7-16 Version 1.0...
Page 232: Extended Wait Transfers
NAND Flash control pins. Connection of the SoC to the NAND Flash is illustrated in Figure 7-14. During boot, the Boot ROM in the LH79524/LH79525 automatically controls the logic to present the proper signals at the proper times on the address lines acting as control sig- nals.
Page 233: Table 7-2. Boot Configuration For Silicon Version A.0
External Memory Controller LH79524/LH79525 User’s Guide Table 7-2. Boot Configuration for Silicon Version A.0 PC[7:4] DEVICE TYPE DATA BUS WIDTH CONTROL nBLEx LOW for Reads NOR Flash or SRAM 16-bit NOR Flash or SRAM 16-bit nBLEx HIGH for Reads NOR Flash or SRAM...
Page 234: Figure 7-14. Connection To Nand Flash
LH79524/LH79525 User’s Guide External Memory Controller nCS0 LH79524/ NAND LH79525 FLASH nFWE nFRE D[15:0] IO[15:0] DATA/ADDRESS/COMMAND D[7:0] IO[7:0] LH79525-115 Figure 7-14. Connection to NAND Flash Version 1.0 7-19...
Page 235: Table 7-4. 16-Bit Address Mapping
External Memory Controller LH79524/LH79525 User’s Guide 7.3.2 General NAND Flash Access At all other times but boot, all address lines function as addresses, and the NAND Flash control signals must be generated by the application software. Unlike booting, where the internal boot code automatically translates the addresses as required by the data width, in general application use, the software must perform this translation prior to writing to the NAND Flash.
Page 236: Figure 7-15. Nand Flash Timing Example
With all control signals FALSE, the address of the location to be written in the NAND Flash is placed on the LH79524/LH79525 D[15:0] pins (‘A’ in the Figure). Software, with the proper signals on D[15:0], then programs a Write to location 0xCXXX10, causing ALE and nFWE to go HIGH (‘B’).
Page 237: Table 7-5. 32-Bit Wide Data Bus Address Mapping, Sdram (Rbc)
External Memory Controller LH79524/LH79525 User’s Guide 7.4 Dynamic Memory 7.4.1 Write-protection Each dynamic memory Chip Select can be configured for write-protection by setting the rel- evant bit in the write-protect field in the DYNCFGx register (DYNCFGx:P). If a write access is performed to a write-protected memory bank, an ERROR response is generated on the HRESP[1:0] signal.
Page 238: Table 7-6. 32-Bit Wide Data Bus Address Mapping, Sdram (Brc)
LH79524/LH79525 User’s Guide External Memory Controller Table 7-5. 32-bit Wide Data Bus Address Mapping, SDRAM (RBC) (Cont’d) 32-BIT DEVICE 64M SDRAM (8M × 8, RBC) External Address Pin, A[14:0] AHB Address To Row Address 11/BA1 12/BA0 — AHB Address To Column Address...
Page 239 External Memory Controller LH79524/LH79525 User’s Guide Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC) (Cont’d) 32-BIT DEVICE 64M SDRAM (2M × 32, BRC) External Address Pin, A[14:0] AHB Address To Row Address 21/BA1 22/BA0 — — AHB Address To Column Address...
Page 240: Table 7-7. 16-Bit Wide Data Bus Address Mapping, Sdram (Rbc)
LH79524/LH79525 User’s Guide External Memory Controller Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC) 16-BIT WIDE DEVICE 16M SDRAM (1M × 16, RBC) External Address Pin, A[14:0] AHB Address To Row Address 9/BA1 — — — AHB Address To Column Address 9/BA1 —...
Page 241: Table 7-8. 16-Bit Wide Data Bus Address Mapping, Sdram (Brc)
External Memory Controller LH79524/LH79525 User’s Guide Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC) 16-BIT WIDE DEVICE 16M SDRAM (1M × 16, BRC) External Address Pin, A[14:0] AHB Address To Row Address — 20/BA0 — — AHB Address To Column Address —...
Page 242: Table 7-9. Memory System Examples
LH79524/LH79525 User’s Guide External Memory Controller 7.4.4 Data Mask Signals Depending on the external memory system width and the operand size, one or two mem- ory cycles may be required for operand transfer. The Data Mask signals (DQM[3:0]) select the data phase for each cycle, as shown in Table 7-9.
Page 243: Table 7-10. External Memory Controller Register Summary
External Memory Controller LH79524/LH79525 User’s Guide 7.5 Register Reference The base address for the EMC is 0xFFFF1000. 7.5.1 Memory Map Table 7-10 Summarizes the EMC registers. Table 7-10. External Memory Controller Register Summary ADDRESS REGISTER DESCRIPTION OFFSET 0x000 CONTROL Control Register...
Page 244 LH79524/LH79525 User’s Guide External Memory Controller Table 7-10. External Memory Controller Register Summary ADDRESS REGISTER DESCRIPTION OFFSET 0x200 SCONFIG0 Static Memory Configuration for nCS0 0x204 SWAITWEN0 Static Memory Write Enable Delay for nCS0 0x208 SWAITOEN0 Static Memory Output Enable Delay for nCS0...
Page 245: Table 7-11. Control Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2 Register Definitions 7.5.2.1 Control Register (CONTROL) The CONTROL Register controls the memory controller operation. The control bits can be altered during normal operation. Table 7-11. CONTROL Register FIELD RESET TYPE FIELD RESET TYPE...
Page 246: Table 7-13. Status Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.2 Status Register (STATUS) The STATUS Register provides memory controller status information. Table 7-13. STATUS Register FIELD RESET TYPE FIELD RESET TYPE ADDR 0xFFFF1000 + 0x004 Table 7-14. STATUS Fields BITS NAME FUNCTION 31:3 Reserved Reading returns 0.
Page 247: Table 7-15. Config Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.3 Configuration Register (CONFIG) The CONFIG Register configures the operation of the memory controller. This register must only be modified during system initialization, or when there are no cur- rent or outstanding transactions. Software can ensure that there are no current or out- standing transactions by waiting until the memory controller is idle, then entering Low- Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
Page 248: Table 7-17. Dynmctrl Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.4 Dynamic Memory Control Register (DYNMCTRL) The Dynamic Memory Control Register is used to control dynamic memory operation. The control bits can be altered during normal operation. Table 7-17. DYNMCTRL Register FIELD RESET TYPE...
Page 249: Table 7-19. Dynmref Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.5 Dynamic Refresh Register (DYNMREF) This register configures dynamic memory operation. This register should only be modified during system initialization, or when there are no current or outstanding transactions. Software can ensure that there are no current or outstanding transactions by waiting until the memory controller is idle, then entering Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
Page 250: Table 7-21. Dynmrcon Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.6 Dynamic Memory Read Configuration Register (DYNMRCON) This register allows configuration of the dynamic memory Read strategy. This register should only be modified during initialization. This register provides the Read strategy for all four dynamic memory Chip Select signals. The DYNMRCON resets to 0x00, which is invalid.
Page 251: Table 7-23. Precharge Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.7 Dynamic Precharge Command Period Register (PRECHARGE) The Dynamic Memory Precharge Command Period Register programs the Precharge Command Period, tRP. This value is normally found in SDRAM data sheets as tRP. This register must only be modified during system initialization, or when there are no current or outstanding transactions.
Page 252: Table 7-25. Dynm2Pre Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.8 Dynamic Memory Active to Precharge Command Period Register (DYNM2PRE) The Dynamic Memory Active to Precharge Command Period Register enables program- ming the Active to Precharge Command Period, tRAS. This value is normally found in...
Page 253: Table 7-27. Refexit Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.9 Dynamic Memory Self-Refresh Exit Time Register (REFEXIT) The Dynamic Memory Self-Refresh Exit Time Register enables programming the Self-refresh Exit Time, tSREX. This value is normally found in SDRAM data sheets as . This register is used as the self-refresh exit time for all chip selects. Therefore, it SREX must be programmed with the longest exit time period required of all the chip selects.
Page 254: Table 7-29. Doactive Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.10 Dynamic Memory Last Data Out to Active Time Register (DOACTIVE) The Dynamic Memory Last Data Out to Active Time Register enables programming the Last-data-out to Active Command Time, tAPR. This value is normally found in SDRAM data sheets as tAPR.
Page 255: Table 7-31. Diactive Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.11 Dynamic Memory Data-In to Active Time Register (DIACTIVE) The Dynamic Memory Data-In to Active Time Register enables programming the Data-in to Active Command time, tDAL. This value is normally found in SDRAM data sheets as tDAL, or tAPW.
Page 256: Table 7-33. Dwrt Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.12 Dynamic Memory Write Recovery Time Register (DWRT) The Dynamic Memory Write Recovery Time Register enables programming the Write Recovery Time, tWR. This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL.
Page 257: Table 7-35. Dynactcmd Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.13 Dynamic Memory Active to Active Command Period Register (DYNACTCMD) The Dynamic Memory Active to Active Command Period Register enables programming the Active to Active Command Period, tRC. This value is normally found in SDRAM data sheets as tRC.
Page 258: Table 7-37. Dynauto Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.14 Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register (DYNAUTO) The Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register enables programming the Auto-refresh Period, and Auto-refresh to Active Com- mand Period, tRFC.
Page 259: Table 7-39. Dynrefexit Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.15 Dynamic Memory Exit Self-Refresh to Active Command Time Register (DYNREFEXIT) The Dynamic Memory Exit Self-Refresh to Active Command Time Register selects the Exit Self-refresh to Active Command Time, tXSR. This value is normally found in SDRAM data sheets as tXSR.
Page 260: Table 7-41. Dynactiveab Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.16 Dynamic Memory Active Bank A to Active Bank B Time Register (DYNACTIVEAB) The Dynamic Memory Active Bank A to Active Bank B Time Register programs the active bank A to active bank B latency, tRRD. This value is normally found in SDRAM data sheets as tRRD.
Page 261: Table 7-43. Dynamictmrd Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.17 Dynamic Memory Load Mode Register to Active Command Time Register (DYNAMICTMRD) The Dynamic Memory Load Mode Register to Active Command Time Register specifies the Load Mode Register to Active Command Time, tMRD. This value is normally found in SDRAM data sheets as tMRD, or tRSA.
Page 262: Table 7-45. Wait Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.18 Static Memory Extended Wait Register (WAIT) The Static Memory Extended Wait Register is used to time long static memory read and write transfers (longer than can be supported by the SWAITRD or SWAITWR registers) when the EW bit of the SCONFIG register is enabled.
Page 263: Table 7-47. Dyncfgx Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.19 Dynamic Configuration Register for nDCS0 and nDCS1 (DYNCFGx) The Dynamic Configuration Register specifies the configuration information for the rele- vant dynamic memory Chip Select. These registers are normally only modified during sys- tem initialization.
Page 264: Table 7-49. Address Mapping
LH79524/LH79525 User’s Guide External Memory Controller Table 7-49. Address Mapping DYNCFGx BITS DESCRIPTION [14] [12] [11:9] [8:7] 16-BIT EXTERNAL BUS HIGH-PERFORMANCE ADDRESS MAPPING (ROW, BANK, COLUMN) 16Mb (2M × 8), 2 banks, row length = 11, column length = 9 16Mb (1M ×...
Page 265 External Memory Controller LH79524/LH79525 User’s Guide Table 7-49. Address Mapping (Cont’d) DYNCFGx BITS DESCRIPTION [14] [12] [11:9] [8:7] 32-BIT EXTERNAL BUS LOW POWER SDRAM ADDRESS MAPPING (ROW, BANK, COLUMN) 16Mb (2M × 8), 2 banks, row length = 11, column length = 9 16Mb (1M ×...
Page 266: Table 7-50. Dynrascasx Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.20 Dynamic Memory RAS and CAS Delay Register for nDCS0 and nDCS1 (DYNRASCASx) The Dynamic Memory RAS and CAS Delay Register selects the RAS and CAS latencies for the relevant dynamic memory. Note that the same value must be programmed into the device’s Mode register.
Page 267: Table 7-52. Sconfigx Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.21 Static Memory Configuration Register (SCONFIGx) The Static Memory Configuration Registers are used to configure the static memory configuration. These registers must only be modified during system initialization, or when there are no current or outstanding transactions. Software can ensure that there are no current or outstanding transactions by waiting until the memory controller is idle, then entering Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
Page 268 LH79524/LH79525 User’s Guide External Memory Controller Table 7-53. SCONFIGx Fields (Cont’d) BITS NAME FUNCTION Extended Wait Extended wait uses the WAIT register to time both the read and write transfers rather than the SWAITRD and SWAITWR registers. This enables much longer transactions.
Page 269: Table 7-54. Swaitwenx Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.22 Static Memory Write Enable Delay Registers (SWAITWENx) The Static Memory Write Enable Delay Registers allow programming a delay between Address Valid and the assertion of nWE (nBLEx). See Section 7.2.4.1.2 for a complete description of programming these registers.
Page 270: Table 7-56. Swaitoenx Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.23 Static Memory Output Enable Delay Registers (SWAITOENx) The Static Memory Output Enable Delay Registers enable programming the delay from the Valid Address to nOE assertion. See Section 7.2.4.1.1 for a complete description of pro- gramming these registers.
Page 271: Table 7-58. Swaitrdx Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.24 Static Memory Read Delay Registers (SWAITRDx) The Static Memory Read Delay Registers enable programming Read cycle wait states. A complete description of programming this register appears in Section 7.2.4.1.1. The total Read cycle time is the total time that the address is valid. During this time, several parameters are programmable.
Page 272: Table 7-60. Swaitpagex Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.25 Static Memory Page Mode Read Delay Registers (SWAITPAGEx) The Static Memory Page Mode Read Delay Registers enable programming the delay for Asynchronous Page Mode sequential accesses. These registers must only be modified during system initialization, or when there are no current or outstanding transactions.
Page 273: Table 7-62. Swaitwrx Register
External Memory Controller LH79524/LH79525 User’s Guide 7.5.2.26 Static Memory Write Delay Registers (SWAITWRx) The Static Memory Write Delay Registers enable programming the number of Write wait states. See Section 7.2.4.1.2 for a complete description of programming these registers. Wait states behave slightly differently for Write transactions than for Reads. Instead of the length of the Write cycle (tWC) being the sum of the valued programmed into the SWAITWENx and SWAITWRx registers, it has the following relationship (with ‘A’...
Page 274: Table 7-64. Sturnx Register
LH79524/LH79525 User’s Guide External Memory Controller 7.5.2.27 Static Memory Turn Around Delay Registers (STURNx) The Static Memory Turn Around Delay Registers enable programming the number of bus turnaround cycles. These registers must only be modified during system initialization, or when there are no current or outstanding transactions.
Page 275: Chapter 8 - General Purpose Input/Output
The LH79524 and LH79525 have a robust set of General Purpose Input/Output (GPIO) pins that can be used for any required input or output function. The LH79524 has 14 ports, providing 108 pins of GPIO. The LH79525 has 11 ports, with 86 individual pins. All descrip- tions, unless noted, apply to both the LH79524 and LH79525.
Page 276: Table 8-2. Lh79524 Gpio Multiplexing
Table 8-2 and Table 8-3 show the multiplexed functions of each GPIO pin. In the case of Port J and Port M, the reset function is not GPIO, hence those functions are listed in the ‘Multiplexed Function’ column. Table 8-2. LH79524 GPIO Multiplexing CABGA AT RESET...
Page 277 LH79524/LH79525 User’s Guide General Purpose Input/Output Table 8-2. LH79524 GPIO Multiplexing (Cont’d) CABGA AT RESET MULTIPLEXED FUNCTION(S) LCDLP/LCDHRLP LCDDCLK LCDPS LCDCLS LCDDSPLEN/LCDREV LCDVDDEN LCDVEEN/LCDMOD nWAIT/nDEOT LCDVD6 LCDVD7 LCDVD8 LCDVD9 LCDVD10 LCDVD11 LCDEN/LCDSPL LCDFP/LCDSPS ETHERTXEN ETHERTXCLK LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDVD4...
Page 278 General Purpose Input/Output LH79524/LH79525 User’s Guide Table 8-2. LH79524 GPIO Multiplexing (Cont’d) CABGA AT RESET MULTIPLEXED FUNCTION(S) LCDVD14 LCDVD15 LCDVD12 LCDVD13 AN3/LR/Y- AN4/WIPER AN2/LL/Y+ PJ5/INT5 PJ6/INT6 PJ7/INT7 nCS0 nCS1 nCS2 nCS3 nBLE0 nBLE1 nBLE2 nBLE3 Version 1.0...
Page 279: Table 8-3. Lh79525 Gpio Multiplexing
LH79524/LH79525 User’s Guide General Purpose Input/Output Table 8-3. LH79525 GPIO Multiplexing AT RESET MULTIPLEXED FUNCTION INT2/UARTRX2/UARTIRRX2 INT3/UARTTX2/UARTIRTX2 CTCAP0A/CTCMP0A CTCAP0B/CTCMP0B CTCAP1A/CTCMP1A CTCAP1B/CTCMP1B CTCAP2A/CTCMP2A/SDA CTCAP2B/CTCMP2B/SCL nDACK/nUARTCTS0 DREQ/nUARTRTS0 SSPFRM/I2SWS SSPCLK/I2SCLK SSPRX/I2SRXD/UARTRX1/UARTIRRX1 SSPTX/I2STXD/UARTTX1/UARTIRTX1 INT0/UARTRX0/UARTIRRX0 INT1/UARTTX0/UARTIRTX0 A22/nFWE A23/nFRE LCDLP/LCDHRLP LCDDCLK LCDPS LCDCLS LCDDSPLEN/LCDREV LCDVDDEN LCDVEEN/LCDMOD...
Page 280 General Purpose Input/Output LH79524/LH79525 User’s Guide Table 8-3. LH79525 GPIO Multiplexing (Cont’d) AT RESET MULTIPLEXED FUNCTION LCDVD10 LCDVD11 LCDEN/LCDSPL LCDFP/LCDSPS ETHERTXEN ETHERTXCLK LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDVD4 LCDVD5 ETHERRX3 ETHERRXDV ETHERRXCLK ETHERTXER ETHERTX0 ETHERTX1 ETHERTX2 ETHERTX3 ETHERMDC ETHERMDIO ETHERCOL ETHERCRS...
Page 281: Table 8-4. Gpio Port Memory Map
LH79524/LH79525 User’s Guide General Purpose Input/Output 8.2 Register Reference This section describes the location and programming of the GPIO registers. Registers are denoted with an ‘x’ that is replaced with the port letter of the register. For example, the Port A Data Direction Register is P1DDRA.
Page 282: Table 8-5. P1Drx Register
• The current value on the corresponding port pin if configured as an input. Port K is only available on the LH79524. Port M is an output only port. This register will not input values from the Port M pins.
Page 283: Table 8-7. P2Drx Register
Reserved Reading this field returns 0. Write the reset value. Port Input/Output Data Contains the bit-by-bit Port input or output data, depending on how the corresponding bit in the P1DDRx Register is PORT_DATA programmed. Note that Port N consists of 4 bits and exists on LH79524 only. Version 1.0...
Page 284: Table 8-9. P1Ddrx Register
Port E: 0xFFFDD000 + 0x08 ADDR Port G: 0xFFFDC000 + 0x08 Port I: 0xFFFDB000 + 0x08 Port K: 0xFFFDA000 + 0x08 (LH79524 Only) Port M: 0xFFFD9000 + 0x08 (Bits 7 and 6 LH79524 Only) Table 8-10. P1DDRx Fields BITS NAME DESCRIPTION 31:8 Reserved Writing to these bits has no effect.
Page 285: Table 8-11. P2Ddrx Register
Port B: 0xFFFDF000 + 0x0C Port D: 0xFFFDE000 + 0x0C Port F: 0xFFFDD000 + 0x0C ADDR Port H: 0xFFFDC000 + 0x0C Port L: 0xFFFDA000 + 0x0C (LH79524 Only) Port N: 0xFFFD9000 + 0x0C (LH79524 Only) Table 8-12. P2DDRx Register Definitions BITS NAME...
Page 286 General Purpose Input/Output LH79524/LH79525 User’s Guide 8-12 Version 1.0...
Page 287: Chapter 9 - I 2 C Module
Chapter 9 C Module The I C Module implements the Inter-IC bus (I C), and provides: • Two-wire synchronous serial interface • Operation in both the standard mode, for data rates up to 100 Mbits/s, and the fast mode, with data rates up to 400 Mbits/s •...
Page 288: Figure 9-2. I 2 C Bus Protocol
C Module LH79524/LH79525 User’s Guide 9.1 Theory of Operation The LH79524/LH79525 implements a two-wire I C Module capable of operating in either Master or Slave mode. The block conforms to the I C 2.1 Bus Specification for data rates up to 400 kbps. The two wires (pins) in the interface are SCL (serial clock) and SDA (serial data).
Page 289 LH79524/LH79525 User’s Guide C Module 9.1.1 Setting I C Clock Timing When the I C Module is in Master mode, the serial clock (SCL) is generated from HCLK, using two registers, ICHCNT and ICLCNT for timing parameters. When the I C Module is in Slave mode, SCL is provided by the Master.
Page 290: Interrupt Handling
C Module LH79524/LH79525 User’s Guide 9.1.2 Interrupt Handling In Slave mode, the I C Module handles address comparison, shifts data into or out of the ICDATA register, and generates ACK pulses at the appropriate times. In short, the inter- face hardware handles the bit-level operation of the protocol.
Page 291: Slave Mode
LH79524/LH79525 User’s Guide C Module 9.1.3 Slave Mode In slave-receiver mode, the I C Module interrupts the processor whenever an address or data byte has been received. The sequence is that the byte is received and acknowledged by the I C Module, then the processor is interrupted.
Page 292: Table 9-3. I 2 C Register Summary
C Module LH79524/LH79525 User’s Guide 9.2 Register Reference This section provides the I C Module register memory mapping and bit fields. 9.2.1 Memory Map The base address for the I C Module is 0xFFFC5000. Table 9-3 summarizes the C Module registers.
Page 293: Table 9-4. Iccon Register
LH79524/LH79525 User’s Guide C Module 9.2.2 Register Definitions 9.2.2.1 I C Configuration Register (ICCON) The ICCON register allows controlling the operating mode of the I C Module, operating parameters, and contains the flags used to start a transfer and to set the data direction.
Page 294: Table 9-6. Icsar Register
C Module LH79524/LH79525 User’s Guide Table 9-5. ICCON Fields (Cont’d) BITS NAME DESCRIPTION Fast/Standard Speed Use this bit to set the transaction speed of the I C Module. SPEED 1 = Fast interface speed (400 kbit/s) 0 = Standard interface speed (100 kbit/s) C Enable This bit turns the I C Module on and off.
Page 295: Table 9-8. Icusar Register
LH79524/LH79525 User’s Guide C Module 9.2.2.3 I C Upper Slave Address Register (ICUSAR) Software programs the ICUSAR register with the upper 2 address bits in 10-bit addressing mode, plus the read/write data direction (SRW) bit. This register is not used in Master mode.
Page 296: Table 9-12. Ichcnt Register
C Module LH79524/LH79525 User’s Guide 9.2.2.5 I C Clock High Time Register (ICHCNT) The ICHCNT register allows programming the length of the serial clock HIGH time. Table 9-12. ICHCNT Register FIELD RESET TYPE FIELD HCNT RESET TYPE ADDR 0xFFFC5000 + 0x10 Table 9-13.
Page 297: Table 9-16. Icstat Register
LH79524/LH79525 User’s Guide C Module 9.2.2.7 I C Status Register (ICSTAT) The ICSTAT register provides status regarding the state of the module. Table 9-16. ICSTAT Register FIELD RESET TYPE FIELD RESET TYPE ADDR 0xFFFC5000 + 0x1C Table 9-17. ICSTAT Fields...
Page 298 C Module LH79524/LH79525 User’s Guide Table 9-17. ICSTAT Fields (Cont’d) BITS NAME DESCRIPTION Full Flag Indicates that a byte of address or data has been received on the I C bus and written into the ICDATA register. This bit remains 1 until automatically cleared when the ICDATA Register is read by software or until the TXABORT bit is set to 1.
Page 299 Chapter 10 S Converter The Synchronous Serial Port (SSP) to I S converter is an interface that converts a syn- chronous serial communication stream in TI DSP-compatible mode into an I S compliant synchronous serial stream. The I S converter operates on serial data in both master and slave mode.
Page 300 S Converter LH79524/LH79525 User’s Guide WS DELAY SSPFSSOUT STROBE (MASTER) CONVERSION WS INVERSION MASTER SSP PULSE > SSP SSPFSS_I2SWS_OUT CLOCK S LEVEL (MASTER) ENABLE 1 CLOCK DELAY WSDEL SSP/I WSINV MODE SSPTXD 1 CLOCK SSPTX_I2STXD_OUT MASTER DELAY CLOCK ENABLE FRAME...
Page 301: Figure 10-2. Ti Ssp Frame Format
LH79524/LH79525 User’s Guide S Converter 10.1 Theory of Operation 10.1.1 Conversion The SSP-to-I S converter converts a data stream from the TIDSP format to the I S for- mat on transmit or from I S format to TI DSP format on receive. The TI DSP format is sup- ported by the SSP block and is fully described in the SSP Chapter.
Page 302: Figure 10-4. Driving/Latching Diagram
S Converter LH79524/LH79525 User’s Guide The I S converter operates in both Master and Slave Modes. In Master Mode, the clock and word select inputs (SSPCLKOUT and SSPFSSOUT) are supplied by the SSP block. In slave mode, the clock and word select inputs are supplied by the external CODEC via the PB3/SSPCLK/I2SCLK and PB2/SSPFRM/I2SWS pins.
Page 303: Figure 10-5. I 2 S Master Mode Transmission Block Diagram
LH79524/LH79525 User’s Guide S Converter 10.1.3 Transmission 10.1.3.1 Master Mode Transmission During Master Mode transmission, the I S converter supplies the clock, frame output, and data (on the PB5/SSPTX/I2STXD/UARTTX0/UARTIRTX0 pin) to the external CODEC. The Master Mode clock is the SSP master mode clock, SSPCLKOUT, inverted as indi- cated by the CTRL:CLKINV bit.
Page 304: Figure 10-7. I 2 S Slave Mode Transmission Block Diagram
S Converter LH79524/LH79525 User’s Guide 10.1.3.2 Slave Mode Transmission During Slave Mode transmission, the I S converter receives its clock (PB3/SSPCLK/I2SCLK) and frame input (PB2/SSPFRM/I2SWS) from the external CODEC. In response to the exter- nal CODEC signals, the I S transmits data on the PB5/SSPTX/I2STXD/UARTTX0/ UARTIRTX0 pin.
Page 305: Figure 10-8. I 2 S Slave Mode Transmission Timing Diagram
LH79524/LH79525 User’s Guide S Converter I2SCLKIN I2SFSSIN EXPECTED I2STXD MSB1 LSB1 MSB2 LSB2 MSB3 (WSDEL = 0) EXPECTED I2STXD MSB1 LSB1 MSB2 LSB2 MSB3 (WSDEL = 1) SSPFSSIN (WSDEL = 0) SSPTXD MSB1 LSB1 MSB2 LSB2 MSB3 (WSDEL = 0)
Page 306 S Converter LH79524/LH79525 User’s Guide S CONVERTER EXTERNAL CODEC (MASTER) (MASTER) (SLAVE) SSPCLKOUT I2SCLKOUT SSPFSSOUT I2SFSSOUT SSPTXD I2SRXD LH79525-99 Figure 10-9. I S Master Mode Reception Block Diagram I2SCLKOUT SSPFSSOUT EXPECTED MSB1 14 LSB1 MSB2 LSB2 MSB3 LSB3 MSB4 SSPRXD...
Page 307: Slave Mode Reception
LH79524/LH79525 User’s Guide S Converter 10.1.4.2 Slave Mode Reception During Slave Mode reception, the I S converter receives its clock (PB3/SSPCLK/I2SCLK), frame input (PB2/SSPFRM/I2SWS) and data (PB4/SSPRX/I2SRXD/UARTRX0/ UARTIRRX0) from the external CODEC. The slave mode clock received by the SSP...
Page 308: Suppression Of Sspfssin
S Converter LH79524/LH79525 User’s Guide 10.1.5 Suppression of SSPFSSIN The assertion of SSPFSSIN to the SSP is suppressed under the following conditions: • When the channel indicated by the Transmit FIFO differs from the channel expected by the External Codec. Since the I...
Page 309: Interrupts
LH79524/LH79525 User’s Guide S Converter 10.1.7 Interrupts The I S Converter can assert seven types of interrupts. Only the single combined interrupt, I2SINTR, goes to the VIC: • SSPPE — I S SSP Protocol Error Interrupt request (Frame size out of bounds), gener-...
Page 310: Receive Interrupt
S Converter LH79524/LH79525 User’s Guide 10.1.7.4 Receive Interrupt SSPRXINTR is the Receive Interrupt. This interrupt is asserted when there are four or more valid entries in the receive FIFO. The interrupt is cleared by reading the receive FIFO until there are three or fewer entries. This interrupt originates in the SSP.
Page 311: Memory Map
LH79524/LH79525 User’s Guide S Converter 10.2 Register Reference This section describes the registers used in I S Converter. 10.2.1 Memory Map The base address for the I S Converter is 0xFFFC8000. Locations at offsets 0x018 through 0xFFF are reserved and must not be used during normal operation.
Page 312: Table 10-2. Ctrl Register
S Converter LH79524/LH79525 User’s Guide 10.2.2 Register Descriptions Note that SSP register bits duplicated in the I S Converter will lag the SSP version of the bit by one clock. 10.2.2.1 Control Register (CTRL) This register allows control of various I...
Page 313: Table 10-4. Wsinv Functionality
LH79524/LH79525 User’s Guide S Converter 10.2.2.1.1 Implementation of WSDEL WSDEL is used to delay the assertion of the frame input/output. During master mode, if WSDEL = 1, then the frame output from the SSP is delayed by one clock before being asserted on the PB2/SSPFRM/I2SWS pin.
Page 314: Table 10-5. Stat Register
S Converter LH79524/LH79525 User’s Guide 10.2.2.2 Status Register (STAT) This register reports various I S converter functions. All bits are read only. Table 10-5. STAT Register FIELD RESET FIELD TXWS RXWS RESET ADDR 0xFFFC8000 + 0x004 Table 10-6. STAT Register Definitions...
Page 315: Table 10-7. Imsc Register
LH79524/LH79525 User’s Guide S Converter 10.2.2.3 Interrupt Mask Set or Clear Register (IMSC) On a Read, this register gives the current value of the mask on the relevant interrupt. Writ- ing 1 to the particular bit sets the mask, enabling the interrupt to be read. Writing 0 clears the corresponding mask.
Page 316: Table 10-9. Ris Register
S Converter LH79524/LH79525 User’s Guide 10.2.2.4 Raw Interrupt Status Register (RIS) This register provides the current raw status value of the corresponding interrupt prior to masking. Writing has no effect. For each bit, 1 = TRUE and 0 = FALSE.
Page 317: Table 10-11. Mis Register
LH79524/LH79525 User’s Guide S Converter 10.2.2.5 Masked Interrupt Status Register (MIS) This register provides the current masked status value of the corresponding interrupt. Writing has no effect; all bits are read only. For each bit, 1 = TRUE and 0 = FALSE.
Page 318: Table 10-13. Icr Register
S Converter LH79524/LH79525 User’s Guide 10.2.2.6 Interrupt Clear Register (ICR) This register is write only. Writing 1 causes the corresponding interrupt to be cleared. Writing 0 has no effect. The value written cannot be read back. Table 10-13. ICR Register...
Page 319 Chapter 11 I/O Configuration The I/O configuration controls: • Pin Muxing: Provides registers to program the pin muxing on the device. • Pull-up/Pull-down Resistors: Provides registers to control the pull-up and pull-down resistors on certain pins of the chip. 11.1 Theory of Operation The I/O Configuration (IOCON) is an AMBA slave block that connects to the APB.
Page 320: Table 11-1. Iocon Register Summary
I/O Configuration LH79524/LH79525 User’s Guide 11.2 Register Reference This section describes the registers used in I/O configuration. In all cases, when the MUX register is programmed its corresponding Resistor register (if it exists) must be programmed. The Resistor registers are not automatically configured.
Page 321 LH79524/LH79525 User’s Guide I/O Configuration Table 11-1. IOCON Register Summary ADDRESS NAME DESCRIPTION OFFSET 0x70 MUXCTL15 Muxing Control 15 For Pin nBLE0/PM4 0x74 RESCTL15 Resistor Control 15 Assignment for pin nBLE0/PM4 0x78 Reserved Do not access 0x7C Reserved Do not access...
Page 322: Table 11-2. Muxctl1 Register
11.2.2 Register Definitions 11.2.2.1 Multiplexing Control 1 Register (MUXCTL1) This Register allows software to configure pins . Bits PI2/ETHERCOL through PL0/LCDVD14 marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-2. MUXCTL1 Register FIELD RESET FIELD...
Page 323: Table 11-4. Resctl1 Register
I/O Configuration 11.2.2.2 Resistor Configuration Control 1 Register (RESCTL1) The RESCTL1 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-4. RESCTL1 Register...
Page 324: Table 11-6. Muxctl3 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.3 Multiplexing Control 3 Register (MUXCTL3) The MUXCTL3 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-6. MUXCTL3 Register FIELD RESET FIELD INT4 RESET ADDR 0xFFFE5000 + 0x10 Table 11-7. MUXCTL3 Fields...
Page 325: Table 11-10. Muxctl4 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.5 Multiplexing Control 4 Register (MUXCTL4) The MUXCTL4 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-10. MUXCTL4 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x18 Table 11-11. MUXCTL4 Fields NAME...
Page 326: Table 11-12. Resctl4 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.6 Resistor Configuration Control 4 Register (RESCTL4) The RESCTL4 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors Table 11-12. RESCTL4 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x1C Table 11-13. RESCTL4 Fields...
Page 327: Table 11-14. Muxctl5 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.7 Multiplexing Control 5 Register (MUXCTL5) The MUXCTL5 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-14. MUXCTL5 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x20 Table 11-15. MUXCTL5 Fields NAME...
Page 328: Table 11-16. Resctl5 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.8 Resistor Configuration Control 5 Register (RESCTL5) The RESCTL5 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors Table 11-16. RESCTL5 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x24 Table 11-17. RESCTL5 Fields...
Page 329 LH79524/LH79525 User’s Guide I/O Configuration Table 11-17. RESCTL5 Fields (Cont’d) NAME DESCRIPTION Pin PB4/SSPRX/UARTRX1/UARTIRRX1 Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PB3/SSPCLK Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 330: Table 11-18. Muxctl6 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.9 Multiplexing Control 6 Register (MUXCTL6) The MUXCTL6 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-18. MUXCTL6 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x28 Table 11-19. MUXCTL6 Fields BIT NAME...
Page 331: Table 11-20. Resctl6 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.10 Resistor Configuration Control 6 Register (RESCTL6) The RESCTL6 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-20. RESCTL6 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x2C Table 11-21. RESCTL6 Fields...
Page 332: Table 11-22. Muxctl7 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.11 Multiplexing Control 7 Register (MUXCTL7) The MUXCTL7 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-22. MUXCTL7 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x30 Table 11-23. MUXCTL7 Fields NAME...
Page 333 LH79524/LH79525 User’s Guide I/O Configuration Table 11-23. MUXCTL7 Fields (Cont’d) NAME DESCRIPTION PC2/A18 Assignment 00 = PC2 01 = A18 10 = Reserved 11 = Reserved PC1/A17 Assignment 00 = PC1 01 = A17 10 = Reserved 11 = Reserved...
Page 334: Table 11-24. Resctl7 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.12 Resistor Configuration Control 7 Register (RESCTL7) The RESCTL7 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-24. RESCTL7 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x34 Table 11-25. RESCTL7 Fields...
Page 335 LH79524/LH79525 User’s Guide I/O Configuration Table 11-25. RESCTL7 Fields (Cont’d) NAME DESCRIPTION Pin PC2/A18 Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PC1/A17 Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 336: Table 11-26. Muxctl10 Register
LH79524/LH79525 User’s Guide 11.2.2.13 Multiplexing Control 10 Register (MUXCTL10) The MUXCTL10 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-26. MUXCTL10 Register FIELD...
Page 337 LH79524/LH79525 User’s Guide I/O Configuration Table 11-27. MUXCTL10 Fields (Cont’d) NAME DESCRIPTION PK6/D22 Assignment (LH79524 Only) 00 = PK6 01 = D22 10 = Reserved 11 = Reserved PD5/D13 Assignment 00 = PD5 01 = D13 10 = Reserved 11 = Reserved...
Page 338: Table 11-28. Resctl10 Register
LH79524/LH79525 User’s Guide 11.2.2.14 Resistor Configuration Control 10 Register (RESCTL10) The RESCTL10 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-28. RESCTL10 Register...
Page 339 LH79524/LH79525 User’s Guide I/O Configuration Table 11-29. RESCTL10 Fields (Cont’d) NAME DESCRIPTION Pin PK6/D22 Resistor Assignment (LH79524 Only) 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PD5/D13 Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 340: Table 11-30. Muxctl11 Register
LH79524/LH79525 User’s Guide 11.2.2.15 Multiplexing Control 11 Register (MUXCTL11) The MUXCTL11 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-30. MUXCTL11 Register FIELD...
Page 341 NAME DESCRIPTION PD2/D10 Assignment 00 = PD2 01 = D10 10 = Reserved 11 = Reserved PK2/D18 Assignment (LH79524 Only) 00 = PK2 01 = D18 10 = Reserved 11 = Reserved PK1/D17 Assignment (LH79524 Only) 00 = PK1 01 = D17...
Page 342: Table 11-32. Resctl11 Register
LH79524/LH79525 User’s Guide 11.2.2.16 Resistor Configuration Control 11 Register (RESCTL11) The RESCTL11 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-32. RESCTL11 Register...
Page 343 LH79524/LH79525 User’s Guide I/O Configuration Table 11-33. RESCTL11 Fields (Cont’d) NAME DESCRIPTION Pin PK2/D18 Resistor Assignment (LH79524 Only) 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PK1/D17 Resistor Assignment (LH79524 Only) 00 = No Pull-Down or Pull-Up...
Page 344: Table 11-34. Muxctl12 Register
LH79524/LH79525 User’s Guide 11.2.2.17 Multiplexing Control 12 Register (MUXCTL12) The MUXCTL12 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-34. MUXCTL12 Register FIELD...
Page 345: Table 11-36. Resctl12 Register
I/O Configuration 11.2.2.18 Resistor Configuration Control 12 Register (RESCTL12) The RESCTL12 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-36. RESCTL12 Register...
Page 346 I/O Configuration LH79524/LH79525 User’s Guide Table 11-37. RESCTL12 Fields (Cont’d) NAME DESCRIPTION Pin PD4 Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PD3 Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 347: Table 11-38. Resctl13 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.19 Resistor Configuration Control 13 Register (RESCTL13) The RESCTL13 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-38. RESCTL13 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0x64 Table 11-39. RESCTL13 Fields...
Page 348: Table 11-40. Muxctl14 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.20 Multiplexing Control 14 Register (MUXCTL14) The MUXCTL14 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-40. MUXCTL14 Register FIELD RESET FIELD nCS3 nCS2 nCS1 nCS0 nBLE3 nBLE2 nBLE1 LH79525 RESET LH79524...
Page 349 LH79524/LH79525 User’s Guide I/O Configuration Table 11-41. MUXCTL14 Fields (Cont’d) NAME DESCRIPTION nBLE2/PM6 Assignment 00 =nBLE2 nBLE2 01 = PM6 10 = Reserved 11 = Reserved nBLE3/PM5 Assignment 00 =nBLE1 nBLE1 01 = PM5 10 = Reserved 11 = Reserved Version 1.0...
Page 350: Table 11-42. Muxctl15 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.21 Multiplexing Control 15 Register (MUXCTL15) The MUXCTL15 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-42. MUXCTL15 Register FIELD RESET FIELD nBLE0 RESET ADDR 0xFFFE5000 + 0x70 Table 11-43. MUXCTL15 Fields...
Page 351: Table 11-46. Resctl17 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.23 Resistor Configuration Control 17 Register (RESCTL17) The RESCTL17 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-46. RESCTL17 Register FIELD RESET FIELD SDCLK RESET ADDR 0xFFFE5000 + 0x84 Table 11-47. RESCTL17 Fields...
Page 352: Table 11-48. Muxctl19 Register
LH79524/LH79525 User’s Guide 11.2.2.24 Multiplexing Control 19 Register (MUXCTL19) The MUXCTL19 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-48. MUXCTL19 Register FIELD...
Page 353 01 = LCDSPLEN 10 = LCDREV 11 = Reserved PE3/LCDCLS Assignment 00 = PE3 01 = LCDCLS 10 = Reserved 11 = Reserved PL5/D29 Assignment (LH79524 Only) 00 = PL5 01 = D29 10 = Reserved 11 = Reserved Version 1.0 11-35...
Page 354: Table 11-50. Resctl19 Register
LH79524/LH79525 User’s Guide 11.2.2.25 Resistor Configuration Control 19 Register (RESCTL19) The RESCTL19 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-50. RESCTL19 Register...
Page 355 Pin PE3/LCDCLS Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PL5/D29 Resistor Assignment (LH79524 Only) 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Version 1.0...
Page 356: Table 11-52. Muxctl20 Register
LH79524/LH79525 User’s Guide 11.2.2.26 Multiplexing Control 20 Register (MUXCTL20) The MUXCTL20 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-52. MUXCTL20 Register FIELD...
Page 357 LH79524/LH79525 User’s Guide I/O Configuration Table 11-53. MUXCTL20 Fields (Cont’d) NAME DESCRIPTION PN0/D26 Assignment (LH79524 Only) 00 = PN0 01 = D26 10 = Reserved 11 = Reserved PF7/LCDFP/LCDSPS Assignment 00 = PF6 01 = LCDFP 10 = LCDSPS 11 = Reserved...
Page 358: Table 11-54. Resctl20 Register
LH79524/LH79525 User’s Guide 11.2.2.27 Resistor Configuration Control 20 Register (RESCTL20) The RESCTL20 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-54. RESCTL20 Register...
Page 359 LH79524/LH79525 User’s Guide I/O Configuration Table 11-55. RESCTL20 Fields (Cont’d) NAME DESCRIPTION Pin PN0/D26 Resistor Assignment (LH79524 Only) 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PF7/LCDFP/LCDSPS Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 360: Table 11-56. Muxctl21 Register
LH79524/LH79525 User’s Guide 11.2.2.28 Multiplexing Control 21 Register (MUXCTL21) The MUXCTL21 Register allows software to configure a number of LH79524/LH79525 pins. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-56. MUXCTL21 Register FIELD...
Page 361: Table 11-58. Resctl21 Register
I/O Configuration 11.2.2.29 Resistor Configuration Control 21 Register (RESCTL21) The RESCTL21 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Bits marked ‘LH79524 Only’ read as 0 with all writes ‘reserved’ on the LH79525. Table 11-58. RESCTL21 Register...
Page 362: Table 11-60. Muxctl22 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.30 Multiplexing Control 22 Register (MUXCTL22) The MUXCTL22 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-60. MUXCTL22 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xA8 Table 11-61. MUXCTL22 Fields NAME...
Page 363 LH79524/LH79525 User’s Guide I/O Configuration Table 11-61. MUXCTL22 Fields (Cont’d) NAME DESCRIPTION PG4/LCDVD2 Assignment 00 = PG4 01 = LCDVD2 10 = Reserved 11 = Reserved PG3/LCDVD1 Assignment 00 = PG3 01 = LCDVD1 10 = Reserved 11 = Reserved...
Page 364: Table 11-62. Resctl22 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.31 Resistor Configuration Control 22 Register (RESCTL22) The RESCTL22 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-62. RESCTL22 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xAC Table 11-63. RESCTL22 Fields...
Page 365 LH79524/LH79525 User’s Guide I/O Configuration Table 11-63. RESCTL22 Fields (Cont’d) NAME DESCRIPTION Pin PG4/LCDVD2 Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PG3/LCDVD1 Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 366: Table 11-64. Muxctl23 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.32 Multiplexing Control 23 Register (MUXCTL23) The MUXCTL23 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-64. MUXCTL23 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xB0 Table 11-65. MUXCTL23 Fields NAME...
Page 367 LH79524/LH79525 User’s Guide I/O Configuration Table 11-65. MUXCTL23 Fields (Cont’d) NAME DESCRIPTION PH4/ETHERTX0 Assignment 00 = PH4 01 = ETHERTX0 10 = Reserved 11 = Reserved PH3/ETHERTXER Assignment 00 = PH3 01 = ETHERTXER 10 = Reserved 11 = Reserved...
Page 368: Table 11-66. Resctl23 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.33 Resistor Configuration Control 23 Register (RESCTL23) The RESCTL23 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-66. RESCTL23 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xB4 Table 11-67. RESCTL23 Fields...
Page 369 LH79524/LH79525 User’s Guide I/O Configuration Table 11-67. RESCTL23 Fields (Cont’d) NAME DESCRIPTION Pin PH4/ETHERTX0 Resistor Assignment 00 = No Pull-Down or Pull-Up 01 = Pull-Down 10 = Pull-Up 11 = Reserved Pin PH3/ETHERTXER Resistor Assignment 00 = No Pull-Down or Pull-Up...
Page 370: Table 11-68. Muxctl24 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.34 Multiplexing Control 24 Register (MUXCTL24) The MUXCTL24 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-68. MUXCTL24 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xB8 Table 11-69. MUXCTL24 Fields NAME...
Page 371: Table 11-70. Resctl24 Register
LH79524/LH79525 User’s Guide I/O Configuration 11.2.2.35 Resistor Configuration Control 24 Register (RESCTL24) The RESCTL24 Register allows software to configure a number of the LH79524/LH79525 pull-up/pull-down resistors. Table 11-70. RESCTL24 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xBC Table 11-71. RESCTL24 Fields...
Page 372: Table 11-72. Muxctl25 Register
I/O Configuration LH79524/LH79525 User’s Guide 11.2.2.36 Multiplexing Control 25 Register (MUXCTL25) The MUXCTL25 Register allows software to configure a number of LH79524/LH79525 pins. Table 11-72. MUXCTL25 Register FIELD RESET FIELD RESET ADDR 0xFFFE5000 + 0xC0 Table 11-73. MUXCTL25 Fields NAME...
Page 373: Table 11-73. Muxctl25 Fields
LH79524/LH79525 User’s Guide I/O Configuration Table 11-73. MUXCTL25 Fields (Cont’d) NAME DESCRIPTION AN9/PJ2 Assignment 00 = AN9 01 = PJ2 10 = Reserved 11 = Reserved AN4/WIPER/PJ1 Assignment 00 = AN4/WIPER 01 = PJ1 10 = Reserved 11 = Reserved...
Page 374 I/O Configuration LH79524/LH79525 User’s Guide 11-56 Version 1.0...
Page 375: Figure 12-1. Rtc Block Diagram
RTC count matches a programmed value. Figure 12-1 shows a block diagram of the RTC. The RTC is identical in both the LH79524 and LH79525; all descriptions in this chapter apply to both SoCs.
Page 376: Configuring The Rtc For Use
Real Time Clock LH79524/LH79525 User’s Guide The value of the counter can be read by software from the Data Register (DR). This value changes every second. The RTC can be programmed to generate the RTC Interrupt when a value, programmed into the Match Register (MR), is reached. Program the Load Register (LR) to the timing start value.
Page 377: Table 12-1. Rtc Register Summary
LH79524/LH79525 User’s Guide Real Time Clock 12.2 Register Reference 12.2.1 Memory Map The base address for the RTC is: 0xFFFE0000 Table 12-1. RTC Register Summary ADDRESS NAME DESCRIPTION OFFSET 0x00 Data Register 0x04 Match Register 0x08 Load Register 0x0C Control Register...
Page 378: Table 12-4. Mr Register
Real Time Clock LH79524/LH79525 User’s Guide 12.2.2.2 Match Register (MR) MR is the Match Register. Program the value at which the RTC Interrupt will be generated into this register. The difference between this value and the value in the Load Register is the time in seconds, between count initiation and interrupt generation.
Page 379: Table 12-8. Cr Register
LH79524/LH79525 User’s Guide Real Time Clock 12.2.2.4 Control Register (CR) CR allows software to enable the RTC and determine its operational status. Table 12-8. CR Register FIELD RESET FIELD RESET ADDR 0xFFFE0000 + 0x0C Table 12-9. CR Fields NAME DESCRIPTION 31:1 Reserved Unpredictable values when read.
Page 380: Table 12-12. Ris Register
Real Time Clock LH79524/LH79525 User’s Guide 12.2.2.6 Raw Interrupt Status Register (RIS) Reading this register gives the current raw status value of the RTC interrupt prior to mask- ing. Writing has no effect. Table 12-12. RIS Register FIELD RESET FIELD...
Page 381: Table 12-16. Icr Register
LH79524/LH79525 User’s Guide Real Time Clock 12.2.2.8 Interrupt Clear Register (ICR) Writing 1 to the ICR bit clears the RTC interrupt. Writing 0 has no effect. This register can- not be read. Table 12-16. ICR Register FIELD RESET FIELD RESET —...
Page 382 Chapter 13 Reset, Clock, and Power Controller The Reset, Clock, and Power Controller (RCPC) manages the operating mode, generates appropriately prescaled clocks, and correctly times reset execution. The RCPC: • Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep, Stop1, and Stop2 •...
Page 383: Figure 13-1. Rcpc Block Diagram
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide SYSTEM CLOCK OSCILLATOR 32.768 kHz OSCILLATOR PLL CLOCK CLOCK CONTROL BLOCK SYSTEM CLOCK CPU CLOCK ON-CHIP PERIPHERAL CLOCKS ADVANCED PERIPHERAL AHB CLOCK POWER DOWN BUS (APB) AND PLL INTERFACE MODE/FREQUENCY VECTORED INTERRUPT...
Page 384: System Pll And Usb Pll Reset
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller These modes reduce power consumption as needed, with each mode providing greater power savings. Active Mode is the normal operating mode. The other modes are entered via software control. The RCPC returns to Active Mode upon receiving an interrupt.
Page 385: Figure 13-2. Usb Clock Divider Chain
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide The RCPC and PLL interface guarantee that reprogramming the PLL and System Clocks results in an ordely frequency change. For the USB PLL and other clocks, program the Clock Select and frequency before enabling the peripheral clocks as the RCPC does not guarantee clean clock outputs when changing the clock source or USB PLL frequency.
Page 386: Table 13-1. Lh79524/Lh79525 Clocks And Maximum Frequencies
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies FREQUENCY NAME DESCRIPTION (MAX.) Oscillator Clock External crystal oscillator input; used as the source for the three 20.0 MHz (CLK OSC) UARTs. Also an input to the PLL.
Page 387: Table 13-2. Clock And Enable States For Different Power Modes
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.1.4 Power Modes The RCPC supports five Power Modes: • Active mode • Standby mode • Sleep mode • Stop1 mode • Stop2 mode. Table 13-2 shows which clocks are enabled in the various Power Modes.
Page 388: Stop2 Mode
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.1.4.5 Stop2 Mode Stop2 Mode stops all System Clocks and disables both the PLLs and the System Clock Oscillator that feeds it. However, the 32.768 kHz internal oscillator remains active. This mode is entered when software writes 0b100 to the PWRDWNSEL field of the CTRL Register.
Page 389: Table 13-3. Rcpc Register Summary
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2 Register Reference This section provides the RCPC register memory mapping and bit fields. 13.2.1 Memory Map The base address for the RCPC is: 0xFFFE2000. Table 13-3. RCPC Register Summary ADDRESS NAME...
Page 390: Table 13-4. Ctrl Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.1 Control Register (CTRL) The Control Register allows programming the Power Mode, Clock-Out source, and write protecting RCPC registers. Table 13-4. CTRL Register FIELD RESET FIELD OUTSEL PWRDWNSEL RESET ADDR 0xFFFE2000 + 0x00 Table 13-5.
Page 391: Table 13-6. Chipid Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.2 Identification Register (CHIPID) CHIPID is the Identification Register. This Read Only register contains the last three digits of the part number encoded as a 3 digit Binary Coded Decimal (BCD). The CHIPID register is used in conjunction with the SILICONREV register to provide the SoC part number (CHIPID:PARTNO) and the revision number of the silicon (SILICONREV:REVNO).
Page 392: Figure 13-3. Remap = 0B00
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.3 Remap Control Register (REMAP) This REMAP Register provides a remapping feature for the system memory map. Figure 13-3 through Figure 13-6 show the effects of the REMAP bits. Table 13-8. REMAP Register...
Page 393: Figure 13-4. Remap = 0B01
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 0xFFFFFFFF ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS 0xFFFF1000 RESERVED 0xFFFF0000 ADVANCED PERIPHERAL BUS PERIPHERALS 0xFFFC0000 RESERVED 0xA0000000 BOOT ROM 0x80000000 16KB INTERNAL SRAM 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 EXTERNAL SDRAM 0x20000000 EXTERNAL SDRAM nDCS0...
Page 394: Figure 13-6. Remap = 0B11
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 0xFFFFFFFF ADVANCED HIGH-PERFORMANCE BUS PERIPHERALS 0xFFFF1000 RESERVED 0xFFFF0000 ADVANCED PERIPHERAL BUS PERIPHERALS 0xFFFC0000 RESERVED 0xA0000000 BOOT ROM 0x80000000 16KB INTERNAL SRAM 0x60000000 EXTERNAL STATIC MEMORY 0x40000000 EXTERNAL SDRAM 0x20000000 EXTERNAL SRAM nCS0...
Page 395: Table 13-10. Softreset Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.4 Software Reset Register (SOFTRESET) This register allows software to initiate a System Reset. To reset, software programs 0xDEAD into the lower 16 bits. SOFTRESET resets the entire chip, except the System PLL and the USB PLL.
Page 396: Table 13-12. Rststatus Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.5 Reset Status Register (RSTSTATUS) This register provides the reset status of the SoC, containing both the external reset status and the WDT timeout reset status. Following external reset, the EXT bit is 1 and the WDTO bit is 0.
Page 397: Table 13-14. Rststatusclr Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR) This Write Only register clears the two Reset Status flags in the RSTSTATUS register. Writing 1 to this register causes the corresponding bit in the RSTSTATUS to be cleared to 0.
Page 398: Table 13-16. Sysclkpre Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.7 System Clock Prescaler Register (SYSCLKPRE) HCLK is the System Clock. This register allows a divisor to be programmed that is used to divide the system PLL frequency to derive HCLK. The prescaled HCLK frequency is defined by: ⎛...
Page 399: Table 13-19. Cpuclkpre Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE) FCLK is the CPU Clock. This register allows a divisor to be programmed that is used to divide the system PLL frequency to derive FCLK. The prescaled FCLK frequency is defined by: ⎛...
Page 400: Table 13-22. Pclkctrl0 Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0) This register controls the RTC, UART0, UART1, and UART2 peripheral clocks. Program- ming a bit to 1 disables the corresponding peripheral’s clock. These clocks are more fully described in Table 13-1.
Page 401: Table 13-24. Pclkctrl1 Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.10 Peripheral Clock Control Register 1 (PCLKCTRL1) This register controls the USB, ADC, LCD, and SSP peripheral clocks. Programming a bit to 1 disables the corresponding peripheral’s clock. The SSP Clock, USB Clock, and the LCD Data Clock are more fully described in Table 13-1.
Page 402: Table 13-26. Ahbclkctrl Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.11 AHB Clock Control Register (AHBCLKCTRL) This register controls the AHB clocks to several peripherals. Programming a bit to 1 disables the AHB clock to the corresponding peripheral. Following reset, all AHB clocks are enabled.
Page 403: Table 13-28. Pclksel0 Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0) This register allows selection of the clock source for the UARTs. Table 13-28. PCLKSEL0 Register FIELD RESET FIELD RESET ADDR 0xFFFE2000 + 0x30 Table 13-29. PCLKSEL0 Fields...
Page 404: Table 13-30. Pclksel1 Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.13 Peripheral Clock Select Register 1 (PCLKSEL1) This register allows selection of the clock source for the USB, ADC, and SSP peripherals. Note that the default source for the USB clock following reset is HCLK. For virtually all designs, this must be programmed to the USB PLL following reset.
Page 405: Table 13-32. Siliconrev Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.14 Silicon Revision Register (SILICONREV) The SILICONREV register is used in conjunction with the CHIPID register to provide the SoC part number (CHIPID:PARTNO) and the revision number of the silicon (SILICONREV:REVNO). Table 13-32. SILICONREV Register...
Page 406: Table 13-34. Lcdpre Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.15 LCD Clock Prescaler Register (LCDPRE) The value in this register is used as a divisor for HCLK to derive the LCD Data Clock (LCDDCLK) frequency. Following reset, the prescaler is programmed to pass the clock through without division.
Page 407: Table 13-37. Ssppre Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.16 SSP Clock Prescaler Register (SSPPRE) The value in this register is used as a divisor for the Source Clock to derive the SSP clock (SSPCLK) frequency. The SSP clock source (System Clock Oscillator, or HCLK) is selected with the PCLKSEL1:SSP bit (see Section 13.2.2.13).
Page 408: Table 13-40. Adcpre Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.17 ADC Clock Prescaler Register (ADCPRE) The value in this register is used as a divisor for the Source Clock to derive the ADC clock (ADCCLK) frequency. The ACD clock source (System Clock Oscillator, or HCLK) is selected with the PCLKSEL1:ADC bit (see Section 13.2.2.13).
Page 409: Table 13-43. Usbpre Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.18 USB Clock Prescaler Register (USBPRE) The value in this register is used as a divisor for the clock source to derive the USB clock (USBCLK) frequency. The USB clock source (PLL clock, or HCLK) is selected with the PCLKSEL1:USB bit (see Section 13.2.2.13).
Page 410: Table 13-46. Intconfig Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.19 External Interrupt Configuration Register (INTCONFIG) This register configures the individual external interrupts to be either edge-sensitive or level-sensitive, and either active HIGH or active LOW. Following reset, all bits are 0 and configure the external interrupts to be active LOW, level sensitive.
Page 411 Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide Table 13-47. INTCONFIG Fields BITS NAME DESCRIPTION Configures External Interrupt INT3 00 = Configures INT3 to be a level trigger, active LOW. INT3 01 = Configures INT3 to be a level trigger, active HIGH.
Page 412: Table 13-48. Intclr Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.20 External Interrupt Clear Register (INTCLR) This register individually clears active external interrupts. This register can clear edge- triggered interrupts only. Writing to undefined bits has no effect on the RCPC. Note that the reset state is indeterminate since this is write only.
Page 413: Table 13-50. Coreconfig Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.21 Core Clock Configuration Register (CORECONFIG) This register can be programmed to select either the Standard Mode or the FastBus exten- sion for the ARM720T bus interface. In Standard mode, either a synchronous or asynchro- nous operation can be selected.
Page 414: Table 13-52. Syspllctl Register
LH79524/LH79525 User’s Guide Reset, Clock, and Power Controller 13.2.2.22 System PLL Control Register (SYSPLLCTL) This register controls the System PLL frequency. System PLL frequency is calculated by: × SystemClockOscillatorFrequency SYSLOOPDIV SystemPLLfrequencySystem --------------------------------------------------------------------------------------------------------------------------------------------------- SYSPREDIV The maximum System PLL frequency is 304.819 MHz.
Page 415: Table 13-54. Usbpllctl Register
Reset, Clock, and Power Controller LH79524/LH79525 User’s Guide 13.2.2.23 USB PLL Control Register (USBPLLCTL) This register controls the USB PLL frequency and power down. The USB PLL frequency is calculated by: × ⎛ SystemClockOscillatorFrequency USBLOOPDIV ⎞ -------------------------------------------------------------------------------------------------------------------------------------------------------- - USBPLLFrequency ⎝...
Page 416: Theory Of Operation
Chapter 14 Synchronous Serial Port The Synchronous Serial Port is a master or slave interface that enables synchronous serial communication with slave or master peripherals in one of three modes: • Motorola SPI • Texas Instruments DSP-compatible synchronous serial interface •...
Page 417: Table 14-1. Feature Comparison
Synchronous Serial Port LH79524/LH79525 User’s Guide Table 14-1 describes these modes. Table 14-1. Feature Comparison MODE DESCRIPTION DATA TRANSFERS COMMENT Lets the SSP communicate Clock polarity and phase Full-duplex, 4-wire with Motorola SPI-compatible are programmable. synchronous devices. Lets the SSP communicate...
Page 418: Figure 14-1. Ssp Timing Waveform Parameters
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.1.1 Timing Waveforms Figure 14-1 shows the standard set of SSP timing waveforms. Timing values for the call- outs on the figure can be found in the Data Sheet. Figure 14-1. SSP Timing Waveform Parameters Version 1.0...
Page 419: Figure 14-2. Motorola Spi Frame Format (Continuous Transfer)
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.1.2 Motorola SPI Frame Format For the Motorola SPI format, the serial frame pin (SSPFRM) is active LOW. The SPO and SPH bits in SSP Control Register 0 influence SSPCLK and SSPFRM operation in Single and Continuous Modes.
Page 420: Figure 14-4. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.1.3 Texas Instruments Frame Format For the Texas Instruments DSP-compatible synchronous serial interface frame format, the SSPFRM pin is pulsed for one serial clock period stating at its rising edge, prior to each frame's transmission. For this frame format, the SSP outputs data on the rising edge of the clock and latches input data on the rising edge of the clock.
Page 421: Figure 14-6. Microwire Frame Format (Single Transfer)
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.1.4 National Semiconductor Frame Format Unlike the full-duplex transmission capabilities that the other two frame formats support, the National Semiconductor Microwire format uses a special half-duplex, master-slave messaging technique. In this mode: When a frame begins, an 8-bit control message is transmitted to the off-chip slave.
Page 422: Figure 14-7. Microwire Frame Format (Continuous Transfers)
LH79524/LH79525 User’s Guide Synchronous Serial Port SSPCLK nSSPFRM SSPTXD 8-BIT CONTROL SSPRXD 4 to 16 BITS OUTPUT DATA LH79525-79 Figure 14-7. Microwire Frame Format (Continuous Transfers) 14.1.5 Clock Generation The serial bit rate is derived by dividing down the SSP clock coming from the RCPC that is a prescaled version of the system clock (see the RCPC chapter for detailed infor- mation about setting up the system clock).
Page 423: Chapter 14 - Synchronous Serial Port
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.1.6.2 Transmit Interrupt SSPTXINTR is the Transmit Interrupt. This interrupt is asserted when the FIFO is less than or equal to half full (when there is space for four or more entries). The interrupt is cleared when there are five or more entries in the transmit FIFO.
Page 424: Table 14-2. Ssp Register Summary
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.2 Register Reference This section provides the SSP’s register memory mapping and bit fields. 14.2.1 Memory Map The base address for the SSP is 0xFFFC6000. Locations at offsets 0x028 through 0xFFF are reserved and must not be accessed.
Page 425: Table 14-3. Ctrl0 Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2 Register Descriptions 14.2.2.1 Control Register 0 (CTRL0) This register, defined in Table 14-3 and Table 14-4, enables or disables the SSP and con- trols the serial clock rate, its phase, polarity, data size, and frame format. Bits 3:0 reset to 0b0000 and must be programmed to a valid number prior to using the SSP.
Page 426 LH79524/LH79525 User’s Guide Synchronous Serial Port Table 14-4. CTRL0 Fields BITS NAME DESCRIPTION Data Size Select Program with the correct data block size. 0000 = Undefined Operator 0001 = Undefined Operator 0010 = Undefined Operator 0011 = 4-bit data 0100 = 5-bit data...
Page 427: Table 14-5. Ctrl1 Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2.2 Control Register 1 (CTRL1) CTRL1 is the Control Register 1. CTRL1 contains four bit fields that control various SSP functions. Table 14-5. CTRL1 Register FIELD RESET FIELD RESET ADDR 0xFFFC6000 + 0x004 Table 14-6. CTRL1 Fields...
Page 428: Table 14-7. Dr Register
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.2.2.3 Data Register – Receive/Transmit FIFO Register (DR) DR is the 16-bit-wide Receive/Transmit FIFO register. • When DR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSP's receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer).
Page 429: Table 14-9. Sr Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2.4 Status Register (SR) SR is the Status Register. This register contains bits that indicate the FIFO fill status and the SSP busy status. Table 14-9. SR Register FIELD RESET FIELD BSY REFI RNE...
Page 430: Table 14-11. Cpsr Register
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.2.2.5 Clock Prescale Register (CPSR) The CPSR Register specifies the division factor by which the input HCLK is internally divided before use. The value programmed into this register is a value from 2 to 254. This Because register defaults to zero, but is double buffered and reads back 1s after Reset.
Page 431: Table 14-13. Imsc Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2.6 Interrupt Mask Set and Clear Register (IMSC) IMSC is the Interrupt Mask Set and Clear Register. On a read, this register gives the cur- rent value of the mask on the relevant interrupt. A write of 1 to the particular bit clears the mask, enabling the interrupt to be read.
Page 432: Table 14-15. Ris Register
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.2.2.7 Raw Interrupt Status Register (RIS) This register provides the current raw status value of the corresponding interrupt prior to masking. A write has no effect. Table 14-15. RIS Register FIELD RESET FIELD RESET...
Page 433: Table 14-17. Mis Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2.8 Masked Interrupt Status Register (MIS) MIS is the Masked Interrupt Status Register. When read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. Table 14-17. MIS Register...
Page 434: Table 14-19. Icr Register
LH79524/LH79525 User’s Guide Synchronous Serial Port 14.2.2.9 Interrupt Clear Register (ICR) ICR is the Interrupt Clear Register. This register is write only. On a write of 1, the corre- sponding interrupt is cleared. Writing 0 has no effect. Table 14-19. ICR Register...
Page 435: Table 14-21. Dcr Register
Synchronous Serial Port LH79524/LH79525 User’s Guide 14.2.2.10 DMA Control Register (DCR) DCR is the DMA Control Register. The RXDMAE and TXDMAE bits are not automatically cleared for standard Stream 0 through 3 DMA operations, respectively. These bits should be explicitly cleared by soft- ware as soon as possible following DMA completion.
Page 436 • Timer 1 has two Capture Registers and two Compare Registers. • Timer 2 has two Capture Registers and two Compare Registers. Throughout this chapter, all descriptions apply to both the LH79524 and LH79525. In this chapter there are also a number of registers with similar names and functions. Descrip- tions of these registers refer to the name with an ‘x’...
Page 437: Figure 15-1. Timer Block Diagram
Timers LH79524/LH79525 User’s Guide CTCLK TIMER 0 BLOCK CAPTURE ADVANCED INPUT PERIPHERAL TIMER 0 COUNTER INPUT CAPTURE × 5 BUS (APB) COMPARE OUTPUT INTERRUPT INTERRUPT CONTROL COMPARE REGISTER × 2 REQUEST TIMER 1 BLOCK CAPTURE INPUT TIMER 1 COUNTER INPUT CAPTURE × 2...
Page 438: Figure 15-2. Count Clock Timing (Hclk In Phase With Ctclk)
LH79524/LH79525 User’s Guide Timers Figure 15-2 shows the timing of CTCLK with respect to HCLK when the two are in phase. Figure 15-3 shows the timing of CTCLK with respect to HCLK when the two are not in phase. SYSTEM...
Page 439: Figure 15-4. Capture Signal Synchronization Timing
Timers LH79524/LH79525 User’s Guide 15.1.2 Capture Signal Sampling The capture signal causes the value of the timer to be captured and stored in the Timer Capture Register (TxCAPn) associated with the particular input pin being used. For exam- ple, to sample Timer 0 using a trigger on the CTC0A pin, that count would be stored in the T0CAPA register.
Page 440: Figure 15-5. Pwm Output Signal Timing
LH79524/LH79525 User’s Guide Timers Figure 15-5 shows an example of PWM output signal timing. To implement the timing shown in this Figure, the following values are programmed into the registers. • TxCMP1 = 0x0005 (Period of 6) • TxCMP0 = 0x0001 (Duty Cycle of 2; ‘OFF TIME’ in Figure 15-5) Timer 0 settings: •...
Page 441: Table 15-1. Timer 0 Register Summary
Timers LH79524/LH79525 User’s Guide 15.2 Register Reference This section describes the location and programming of the Timer registers. 15.2.1 Memory Map Register offsets in Table 15-1 are relative to the Timer base address 0xFFFC4000 Table 15-1. Timer 0 Register Summary...
Page 442: Table 15-4. Ctrl0 Register
LH79524/LH79525 User’s Guide Timers 15.2.2 Register Descriptions 15.2.2.1 Timer 0 Control Register (CTRL0) This register allows programming the clock divisor, as well as starting/stopping, and clear- ing the timer count value. Table 15-4. CTRL0 Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x00 Table 15-5.
Page 443: Table 15-6. Cmp_Cap_Ctrl0 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.2 Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0) CMP_CAP_CTRL0 allows programming the operating modes of Timer 0. Table 15-6. CMP_CAP_CTRL0 Register FIELD RESET FIELD CMP1 CMP0 CAPE CAPD CAPC CAPB CAPA RESET ADDR 0xFFFC4000 + 0x04 Table 15-7. CMP_CAP_CTRL0 Register Definitions...
Page 444 LH79524/LH79525 User’s Guide Timers Table 15-7. CMP_CAP_CTRL0 Register Definitions BITS NAME DESCRIPTION Output Value Select Timer/Counter Operation: Programs the value (when a compare match occurs) output on CTCMP0A when the CNT0 Register matches the T0CMP0 Register. 00 = No change occurs to the output CTCMP0A...
Page 445: Table 15-8. Inten0 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.3 Timer 0 Interrupt Control Register (INTEN0) This register allows software to enable and disable individual interrupts as needed. Table 15-8. INTEN0 Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x08 Table 15-9. INTEN0 Register Definitions...
Page 446: Table 15-10. Status0 Register
LH79524/LH79525 User’s Guide Timers 15.2.2.4 Timer 0 Status Register (STATUS0) The Status Register bits contain the raw interrupt status of the various interrupt generators. Raw interrupts reflect the state of the interrupt, whether or not it is enabled. To clear a status bit, write a 1 to that bit.
Page 447: Table 15-12. Cnt0 Register
Timers LH79524/LH79525 User’s Guide Table 15-11. STATUS0 Register Definitions (Cont’d) BITS NAME DESCRIPTION Timer 0 Compare 1 Status CMP1_ST 1 = Read: Interrupt asserted; Write: Clear interrupt 0 = Read: No interrupt asserted; Write: No effect Timer 0 Compare 0 Status CMP0_ST 1 = Read: Interrupt asserted;...
Page 448: Table 15-14. T0Cmpn Registers
LH79524/LH79525 User’s Guide Timers 15.2.2.6 Timer 0 Compare Registers (T0CMPn) There are two T0CMPn Registers for Timer 0. They are designated: • T0CMP0 • T0CMP1 Each register is a 16-bit, read/write register. Contents of these registers are compared continuously with the counter CNT0. When both register and counter values match, the timer responds as programmed in the CMP_CAP_CTRL register.
Page 449: Table 15-16. Capn Register
Timers LH79524/LH79525 User’s Guide 15.2.2.7 Timer 0 Capture Registers (CAPn) There are five CAPn Registers for Timer 0. They are designated: • CAPA • CAPB • CAPC • CAPD • CAPE Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT0 are stored into the associated Capture Register.
Page 450: Table 15-18. Ctrl1 Register
LH79524/LH79525 User’s Guide Timers 15.2.2.8 Timer 1 Control Register (CTRL1) This register allows programming various functions, including PWM Mode, clock selection, and starting/stopping Timer 1. Table 15-18. CTRL1 Register FIELD RESET FIELD CMP1 CMP0 CAPB CAPA RESET ADDR 0xFFFC4000 + 0x30 Table 15-19.
Page 451 Timers LH79524/LH79525 User’s Guide Table 15-19. CTRL1 Register Definitions (Cont’d) BITS NAME DESCRIPTION Output Value Select Timer/Counter Operation: Programs the value (when a compare match occurs) output on CTCMP1A when the CNT1 Register matches the T1CMP0 Register. 00 = No change occurs to the output CTCMP1A...
Page 452: Table 15-20. Inten1 Register
LH79524/LH79525 User’s Guide Timers 15.2.2.9 Timer 1 Interrupt Control Register (INTEN1) This register allows software to enable and disable individual interrupts as needed. Table 15-20. INTEN1 Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x34 Table 15-21. INTEN1 Register Definitions...
Page 453: Table 15-22. Status1 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.10 Timer 1 Status Register (STATUS1) The Status Register bits contain the raw interrupt status of the various interrupt generators. Raw interrupts reflect the state of the interrupt, whether or not it is enabled. To clear a status bit, write a 1 to that bit.
Page 454: Table 15-24. Cnt1 Register
LH79524/LH79525 User’s Guide Timers 15.2.2.11 Timer 1 Counter Register (CNT1) The CNT1 Register is a 16-bit, Read/Write up counter. The counter can be read or written to while it is operating. As a result, counts can be read at any time or the current count can be changed.
Page 455: Table 15-26. T1Cmpn Registers
Timers LH79524/LH79525 User’s Guide 15.2.2.12 Timer 1 Compare Registers (T1CMPn) There are two CMP(n) Registers for Timer 1. They are designated: • T1CMP0 • T1CMP1 Each register is a 16-bit, Read/Write register. Contents of these registers are compared continuously with the counter CNT1. When both register and counter values match, the timer behaves as programmed in the CTRL1 register.
Page 456: Table 15-28. T1Capn Register
LH79524/LH79525 User’s Guide Timers 15.2.2.13 Timer 1 Capture Registers (T1CAPn) There are two T1CAPn Registers for Timer 1. They are designated: • T1CAPA • T1CAPB Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT1 are stored into the associated Capture Register.
Page 457: Table 15-30. Ctrl2 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.14 Timer 2 Control Register (CTRL2) This register allows programming various functions of the timer, including PWM Mode, clock selection, and start/stop. Table 15-30. CTRL2 Register FIELD RESET FIELD CMP1 CMP0 CAPB CAPA RESET ADDR 0xFFFC4000 + 0x50 Table 15-31.
Page 458 LH79524/LH79525 User’s Guide Timers Table 15-31. CTRL2 Register Definitions (Cont’d) BITS NAME DESCRIPTION Output Value Select Timer/Counter Operation: Programs the value (when a compare match occurs) output on CTCMP2A when the CNT2 Register matches the T2CMP0 Register. 00 = No change occurs to the output CTCMP2A...
Page 459: Table 15-32. Inten2 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.15 Timer 2 Interrupt Control Register (INTEN2) This register allows software to enable and disable individual interrupts as needed. Table 15-32. INTEN2 Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x54 Table 15-33. INTEN2 Register Definitions...
Page 460: Table 15-34. Status2 Register
LH79524/LH79525 User’s Guide Timers 15.2.2.16 Timer 2 Status Register (STATUS2) The Status Register bits contain the raw interrupt status of the various interrupt generators. Raw interrupts reflect the state of the interrupt, whether or not it is enabled. To clear a status bit, write a 1 to that bit.
Page 461: Table 15-36. Cnt2 Register
Timers LH79524/LH79525 User’s Guide 15.2.2.17 Timer 2 Counter Register (CNT2) The CNT2 Register is a 16-bit, read/write up counter. The counter can be read or written to while it is operating. As a result, counts can be read at any time or the current count can be changed.
Page 462: Table 15-38. T2Cmpn Registers
LH79524/LH79525 User’s Guide Timers 15.2.2.18 Timer 2 Compare Registers (T2CMPn) There are two T2CMPn Registers for Timer 2. They are designated: • T2CMP0 • T2CMP1 Each register is a 16-bit, Read/Write register. Contents of these registers are compared continuously with the counter CNT2. When both register and counter values match, the timer behaves as programmed in the CTRL2 register.
Page 463: Table 15-40. T2Capn Register
Timers LH79524/LH79525 User’s Guide 15.2.2.19 Timer 2 Capture Registers (T2CAPn) There are two T2CAPn Registers for Timer 2. They are designated: • T2CAPA • T2CAPB Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT2 are stored into the associated Capture Register.
Page 464 Chapter 16 UARTs The LH79524/LH79525 contains three UARTs, UART[2:0]. The UARTs feature: • Character Length: Programmable number of data bits per character (5, 6, 7, or 8). Even, odd, stick, or no-parity bit generation and detection. 1 or 2 Stop bit generation.
Page 465: Figure 16-1. Uart0, Uart1, And Uart2 Block Diagram
UARTs LH79524/LH79525 User’s Guide READ DATA[11:0] WRITE 32 × 9 32 × 12 DATA TRANSMIT RECEIVE FIFO FIFO nUARTRST SYSTEM CLOCK UARTTXD PRESETn CONTROL AND STATUS TRANSMITTER UARTIRTX BAUD16 PSEL BAUD RATE DIVISOR INTERFACE PENABLE REGISTER PWRITE BLOCK BAUD PADDR[11:2]...
Page 466: Transmitting Data
LH79524/LH79525 User’s Guide UARTs 16.1.1 Transmitting Data When the UART is programmed to transmit and enabled, writing data to the transmit FIFO: • Causes the UART to start transmitting a data frame with the parameters indicated in the UARTLCR_H Register. Data continues to be transmitted until the transmit FIFO is empty, as indicated by the Transmit FIFO Empty Flag (UARTFR:TXFE).
Page 467: Nine-Bit Mode
UARTs LH79524/LH79525 User’s Guide 16.1.3 Nine-bit Mode In Nine-bit Mode, the parity bit of the character frame is used to identify the message as containing an address or data (parity is not calculated). Enable Nine-bit Mode by setting bit 9 (9BIT) of UARTLCR_H. Then set or clear bit 8 (ADDTX) to tag the next character written to UARTDR as address (ADDTX=1) or data (ADDTX=0).
Page 468: On-Chip Dma Capabilities
LH79524/LH79525 User’s Guide UARTs 16.1.5 On-Chip DMA Capabilities UART0 can be programmed to utilize the on-chip DMA to reduce processor bandwidth required to service UART activities. DMA functions support burst transfers on the receive channel, transmission channel, or both. When using DMA, the transfer size must be set to 8 bits.
Page 469: Table 16-1. Control Bits To Enable And Disable Hardware Flow Control
UARTs LH79524/LH79525 User’s Guide 16.1.7 Hardware Flow Control Hardware flow control is fully selectable, and allows control of the serial data flow by using the nUARTRTS0 output and nUARTCTS0 input signals. Enabling flow control pins is made in the MUXCTL6:PB1 and MUXCTL6:PB0 fields, which is described in Table 11-18.
Page 470: Table 16-2. Uart Register Summary
LH79524/LH79525 User’s Guide UARTs 16.2 Interrupts UART0, UART1, and UART2 each have a combined interrupt. The individual UART inter- rupt outputs are ORed together to produce the combined interrupt for that UART. Interrupt conditions within the combined interrupt are individually maskable. The Vectored Interrupt Controller (VIC) must be programmed before using the UART interrupts.
Page 471: Table 16-3. Uartdr Register
UARTs LH79524/LH79525 User’s Guide 16.3.2 Register Definitions 16.3.2.1 Data Register (UARTDR) UARTDR is the Data Register for words that are to be transmitted or have been received over the serial interface. Writing to this register initiates transmission from the UART.
Page 472: Table 16-6. Uartrsr/Uartecr Register (Write Operations)
LH79524/LH79525 User’s Guide UARTs Table 16-5. Nine-bit Mode/Parity Bit Table REGISTER:BIT MEANING UARTLCR_H: UARTDR: 9BIT PEAR The parity of the received data character matches the parity selected as de- fined by the EPS and SPS bits in the UARTLCR_H register. In FIFO mode, this error is associated with the character at the top of the FIFO.
Page 473: Table 16-8. Uartrsr/Uartecr Register (Read Operations)
UARTs LH79524/LH79525 User’s Guide Table 16-8 and Table 16-9 describe the UARTRSR/UARTECR Register for Read operations. Table 16-8. UARTRSR/UARTECR Register (Read Operations) FIELD RESET FIELD PEAR RESET UART 0: 0xFFFC0000 + 0x004 ADDR UART 1: 0xFFFC1000 + 0x004 UART 2: 0xFFFC2000 + 0x004 Table 16-9.
Page 474: Table 16-10. Uartfr Register
LH79524/LH79525 User’s Guide UARTs 16.3.2.3 Flag Register (UARTFR) UARTFR is the Flag Register. After System Reset, TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1. Table 16-10. UARTFR Register FIELD RESET FIELD TXFE RXFF TXFF RXFE BUSY...
Page 475: Table 16-12. Uartilpr Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.4 IrDA Low-Power Counter Register (UARTILPR) Program the UARTILPR Register with a divisor value to generate the SIR Baud Clock signal. The UARTILPR Register is reset to 0 and must be reprogrammed with a non-zero divisor value for use. Programming a zero value will result in no SIR Baud Clock pulses being generated.
Page 476: Table 16-14. Uartibrd Register
LH79524/LH79525 User’s Guide UARTs 16.3.2.5 Integer Baud Rate Divisor Register (UARTIBRD) UARTIBRD is the integer portion of the baud rate divisor value. All of the bits in this register clear to 0 on System Reset. Table 16-14. UARTIBRD Register FIELD...
Page 477: Table 16-16. Uartfbrd Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.6 Fractional Baud Rate Divisor Register (UARTFBRD) UARTFBRD is the fractional portion of the baud rate divisor value. Table 16-16. UARTFBRD Register FIELD RESET FIELD FRAC RESET UART 0: 0xFFFC0000 + 0x028 ADDR UART 1: 0xFFFC1000 + 0x028 UART 2: 0xFFFC2000 + 0x028 Table 16-17.
Page 478: Line Control Register (Uartlcr_H)
LH79524/LH79525 User’s Guide UARTs 16.3.2.7 Line Control Register (UARTLCR_H) UARTLCR_H is the Line Control Register. This register is used to configure the UARTs. The contents of the UARTLCR_H Register are not updated until transmission or reception of the current character is complete. Table 16-21 is a truth table for the SPS, EPS, and PEN bits of the UARTLCR_H Register.
Page 479: Table 16-20. Uartlcr_H Fields
UARTs LH79524/LH79525 User’s Guide Table 16-20. UARTLCR_H Fields (Cont’d) NAME DESCRIPTION FIFO Enable Buffers This bit not only enables and disables the FIFO buffers, but also controls the mode. When the FIFO is enabled, it is used to buffer receive and transmit data.
Page 480: Table 16-22. Uartcr Register
LH79524/LH79525 User’s Guide UARTs 16.3.2.8 UART Control Register (UARTCR) UARTCR is the UART Control Register. To enable transmission, bit [8] and bit [0] must be set. Similarly, to enable reception, bit [9] and bit [0] must be set. Table 16-22. UARTCR Register...
Page 481 UARTs LH79524/LH79525 User’s Guide Table 16-23. UARTCR Fields NAME DESCRIPTION Transmit Section Enables the transmit section of the UART. 1 = Transmit section enabled. When the UART is disabled in the middle of transmission, it completes the current character before stopping 0 = Transmit section not enabled Loop Back Enable Places the UART into Loopback Mode.
Page 482: Table 16-24. Uartifls Register
LH79524/LH79525 User’s Guide UARTs 16.3.2.9 Interrupt FIFO Level Select Register (UARTIFLS) UARTIFLS is the Interrupt FIFO Level Select Register. The UARTIFLS Register defines the FIFO level at which interrupts are generated to request service for the receive and transmit FIFOs. The interrupts are generated based on a transition through a level rather than being based on the level;...
Page 483: Table 16-26. Uartimsc Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.10 Interrupt Mask Set/Clear Register (UARTIMSC) UARTIMSC is the Interrupt Mask Register. On a read, this register returns the current value of the mask on the relevant interrupt. Writing 0 to the particular bit masks the interrupt. Writ- ing 1 enables the corresponding interrupt.
Page 484 LH79524/LH79525 User’s Guide UARTs Table 16-27. UARTIMSC Fields (Cont’d) BITS NAME DESCRIPTION Receive Timeout Error Interrupt Mask When read, returns the current mask for the RTIM interrupt. Write values: RTIM 1 = Enable the RTI interrupt 0 = Mask the RTI interrupt Transmit Interrupt Mask When read, returns the current mask for the TXIM interrupt.
Page 485: Table 16-28. Uartris Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.11 Raw Interrupt Status Register (UARTRIS) UARTRIS is the Raw Interrupt Status Register. These values are the state of the interrupt prior to applying the mask specified in the UARTIMSC register. On a read, this register returns the current raw status value of the corresponding interrupt.
Page 486 LH79524/LH79525 User’s Guide UARTs Table 16-29. UARTRIS Fields BITS NAME DESCRIPTION Transmit Interrupt Status Specifies the raw interrupt state of the UARTTXINTR interrupt. TXRIS 1 = Interrupt pending 0 = No interrupt Receive Interrupt Status Specifies the raw interrupt state of the UARTRXINTR interrupt.
Page 487: Table 16-30. Uartmis Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.12 Masked Interrupt Status Register (UARTMIS) UARTMIS is the Masked Interrupt Status Register. On a read, this register returns the cur- rent masked status value of the corresponding interrupt. A write has no effect. Table 16-30. UARTMIS Register...
Page 488 LH79524/LH79525 User’s Guide UARTs Table 16-31. UARTMIS Fields (Cont’d) NAME DESCRIPTION Receive Masked Interrupt Status Specifies the masked interrupt state of the UARTRXINTR interrupt. RXMIS 1 = Interrupt pending 0 = No interrupt, or interrupt masked Reserved Reading returns 0. Write the reset value.
Page 489: Table 16-32. Uarticr Register
UARTs LH79524/LH79525 User’s Guide 16.3.2.13 Interrupt Clear Register (UARTICR) UARTICR is the Interrupt Clear Register. The active bits used in this register are Write Only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Page 490: Table 16-34. Dmactrl Register
LH79524/LH79525 User’s Guide UARTs 16.3.2.14 UART0 DMA Control Register (DMACTRL) UART0 DMACTRL is the UART0 DMA Control Register. It allows control of certain UART DMA functions. The RXDMAEN, and TXDMAEN bits are not automatically cleared for standard Stream 0 through 3 DMA operations, respectively. These bits should be explicitly cleared by soft- ware as soon as possible following DMA completion.
Page 491: Figure 17-1. Usb Block Diagram
Figure 17-1. USB Block Diagram 17.1 Theory of Operation The LH79524 and LH79525 implement a USB Device only. All USB communications are managed by one or more external USB Hosts. The USB Device is identical in both parts, so all descriptions apply to the LH79524 and LH79525.
Page 492: Figure 17-2. Usb Communication Endpoints
Table 17-1 describes the endpoints and their function. Note that the direction type associated with the endpoints is from the perspective of the Host. For example, an IN endpoint terminates a data pipe transferring data from the LH79524/ LH79525 to the Host.
Page 493: Table 17-2. Endpoint Fifo Characteristics
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.1.1.1 Isochronous Endpoints For Isochronous Endpoints, the host generates IN tokens based on the polling interval. The SoC responds to the IN token with data packet. The polling interval is set in the soft- ware driver.
Page 494: Dma Interface
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.1.4 DMA Interface The USB Device includes a six channel DMA Controller with a 64-byte buffer. This section describes the DMA operation and gives programming examples. 17.1.4.1 DMA Modes The DMA controller supports two modes of operation. The operating mode of each channel can be programmed independently.
Page 495: Dma Operation
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.1.5 DMA Operation DMA access to the Endpoint FIFOs requires both the DMA controller and the endpoint to be programmed for the selected DMA Mode. Details are given in the following sections. (It will be helpful to refer to the register descriptions in Section 17.2 before reading these sections.)
Page 496: Dma Mode 1: Out Endpoints
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.1.5.3 DMA Mode 1: OUT Endpoints For operation in DMA Mode 0, these steps describe programming an OUT endpoint: Program the proper interrupt enable bit in the OIE register to 1 to enable that interrupt.
Page 497: Dma Mode 1: In Endpoints
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.1.5.4 DMA Mode 1: IN Endpoints For operation in DMA Mode 1, these steps describe programming an IN endpoint: Program the proper interrupt enable bit in the IN Interrupt Enable (IIE) register to 1 to enable that interrupt.
Page 498: Table 17-3. Usb Register Summary
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2 Register Reference This section provides the USB Device register memory mapping and bit fields. 17.2.1 Memory Map The base address for the USB Device is 0xFFFF5000. Table 17-3 summarizes the USB Device registers.
Page 499 LH79524/LH79525 User’s Guide Universal Serial Bus Device Table 17-3. USB Register Summary (Cont’d) ADDRESS NAME DESCRIPTION OFFSET Number of received bytes in Endpoint 0 FIFO. (INDEX register OUTCOUNT0 set to select Endpoint 0) 0x058 Number of bytes in OUT endpoint FIFO (lower byte). (INDEX reg- OUTCOUNT1 ister set to select Endpoints 1 –...
Page 500: Table 17-4. Far Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.2 Register Definitions 17.2.2.1 Function Address Register (FAR) FAR is a register that should be written with the function’s 7-bit address (received through a SET_ADDRESS descriptor). It is then used for decoding the function address in subse- quent token packets Table 17-4.
Page 501: Table 17-6. Pmr Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.2.2 Power Management Register (PMR) This register is used for SUSPEND, RESUME, and RESET signalling, and for monitoring USB Bus Reset status. Table 17-6. PMR Register FIELD RESET FIELD RESET TYPE ADDR 0xFFFF5000 + 0x004 Table 17-7.
Page 502: Table 17-8. Iir Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.2.3 Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR) IIR is a read-only register that indicates which of the interrupts for IN Endpoints 1, 2, and 3 are currently active. It also indicates whether the Endpoint 0 (the Control Endpoint) inter- rupt is currently active.
Page 503: Table 17-10. Oir Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.2.4 Interrupt Register for OUT Endpoint 1 and 2 (OIR) The OUT Interrupt register (OIR) acts as an interrupt status register for the OUT endpoint EP1 and EP2. Upon interrupt, software should read each of the three interrupt registers (IIR, OIR, and UIR), which clears the interrupt bit.
Page 504: Table 17-12. Uir Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.2.5 Interrupt Register for common USB interrupts (UIR) UIR is a read-only register that indicates which USB interrupts are currently active. All active interrupts will be cleared when this register is read. Table 17-12. UIR Register...
Page 505: Table 17-14. Iie Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.2.6 IN Interrupt Enable Register (IIE) IIE provides interrupt enable bits for the interrupts in IIR. Following reset, all interrupts are enabled. Table 17-14. IIE Register FIELD RESET FIELD RESET TYPE ADDR 0xFFFF5000 + 0x01C Table 17-15.
Page 506: Table 17-16. Oie Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.2.7 OUT Interrupt Enable Register (OIE) OIE provides interrupt enable bits for the interrupts in OIR. Following reset, all interrupts are enabled. Table 17-16. OIE Register FIELD RESET FIELD RESET TYPE ADDR 0xFFFF5000 + 0x024 Table 17-17.
Page 507: Table 17-18. Uie Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.2.8 Interrupt Enable Register (UIE) UIE provides interrupt enable bits for the interrupts in UIR. Following reset, only the USB RESET and the RESUME interrupts are enabled. Table 17-18. UIE Register FIELD RESET...
Page 508: Table 17-20. Frame1 Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.2.9 Frame Number Registers (FRAMEx) The FRAMEx registers store the current USB bus frame number. The frame number com- prises 11 bits. FRAME1 holds the lower eight bits and FRAME2 holds the upper three bits.
Page 509: Table 17-24. Index Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3 Indexed Registers The next group of registers in the USB Device are Indexed. Each IN endpoint and each OUT Endpoint have their own set of control/status registers. Only one set of IN control and status registers and one set of OUT control and status registers appear in the memory map at any one time.
Page 510: Table 17-26. Inmaxp Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.3.2 IN Maximum Packet Size Register (INMAXP) INMAXP defines the maximum packet size for transactions through the currently-selected IN endpoint in units of 8 bytes, except that a value of 128 sets the maximum packet size to 1,023 (the maximum size for an Isochronous packet transferred in a Full-speed trans- action) rather than 1,024.
Page 511: Table 17-28. Csr0 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.3 Control Status Register for EP 0 (CSR0) CSR0 provides control and status bits for Endpoint 0. Table 17-28. CSR0 Register FIELD RESET FIELD RESET TYPE 0xFFFF5000 + 0x044 ADDR (with the INDEX register set to 0) Table 17-29.
Page 512 Universal Serial Bus Device LH79524/LH79525 User’s Guide Table 17-29. CSR0 Fields (Cont’d) BITS NAME FUNCTION Data End Software programs this bit to 1: • After loading the last packet of data into the FIFO, at the same time IN_PKT_RDY is set •...
Page 513: Table 17-30. Incsr1 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.4 Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1) The INCSR1 register maintains the control and status bits for IN endpoints. Software should only access this register for an IN endpoint after the endpoint has been configured via INCSR2.
Page 514 Universal Serial Bus Device LH79524/LH79525 User’s Guide Table 17-31. INCSR1 Fields (Cont’d) BITS NAME FUNCTION FIFO Flush Request Software programs this bit to 1 if it intends to flush the IN FIFO. This bit is programmed to 0 by the USB after the FIFO is flushed (IN_PKT_RDY must be read as a 1 before the USB can program this bit to 0).
Page 515: Table 17-32. Incsr2 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.5 Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2) The INCSR2 register allows software to configure USB access and the function of the IN_PKT_RDY bit. Software should configure endpoints via INCSR2 before reading the INCSR1 register.
Page 516: Table 17-34. Outmaxp Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.3.6 OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP) OUTMAXP is programmed with the maximum packet size for transactions through the cur- rently-selected OUT endpoint — in units of 8 bytes, except that a value of 128 sets the maximum packet size to 1023 (the maximum size for an isochronous packet) rather than 1024.
Page 517: Table 17-36. Outcsr1 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.7 Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1) OUTCSR1 provides control and status bits for transfers through the currently-selected OUT endpoint Table 17-36. OUTCSR1 Register FIELD RESET FIELD RESET TYPE...
Page 518 Universal Serial Bus Device LH79524/LH79525 User’s Guide Table 17-37. OUTCSR1 Fields (Cont’d) BITS NAME FUNCTION Flush OUT FIFO Software programs this bit to 1 to flush the FIFO. This bit can be programmed to 1 only when OUT_PKT_RDY is 1. The packet due to be unloaded by software will be flushed.
Page 519: Table 17-38. Outcsr2 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2) OUTCSR2 provides further control bits for transfers through the currently-selected OUT endpoint Table 17-38. OUTCSR2 Register FIELD RESET FIELD RESET TYPE...
Page 520: Table 17-40. Outcount0 Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.3.9 Count 0 Register (OUTCOUNT0) OUTCOUNT0 is a read-only register that indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned is valid while CSR0:OUT_PKT_RDY is 1. Table 17-40. OUTCOUNT0 Register...
Page 521: Table 17-44. Outcount2 Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.11 Out Count 2 Register (OUTCOUNT2) OUTCOUNT2 is a read-only register that holds the upper 3 bits of the number of received data bytes in the packet in the FIFO associated with the currently-selected OUT endpoint.
Page 522: Table 17-48. Intr Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.3.13 Pending DMA Interrupts Register (INTR) This register indicates the status of pending DMA interrupts Table 17-48. INTR Register FIELD RESET TYPE FIELD RESET TYPE ADDR 0xFFFF5000 + 0x200 Table 17-49. INTR Fields...
Page 523: Table 17-50. Cntlx Register
LH79524/LH79525 User’s Guide Universal Serial Bus Device 17.2.3.14 DMA Channel x Control Register (CNTLx) This register allows configuring various functions for DMA Channels 1 through 6. Table 17-50. CNTLx Register FIELD RESET TYPE FIELD ENDPOINT RESET TYPE Channel 1 = 0xFFFF5000 + 0x204...
Page 524: Table 17-52. Addrx Register
Universal Serial Bus Device LH79524/LH79525 User’s Guide 17.2.3.15 DMA Channel x AHB Memory Address Register Program this register with the AHB memory addresses for each of the six DMA channels. Table 17-52. ADDRx Register FIELD ADDR1 RESET TYPE FIELD ADDR1...
Page 525: Theory Of Operation
Throughout this chapter all descriptions apply to both the LH79524 and LH97525. 18.1 Theory of Operation The VIC provides hardware for initial prioritization and processing of up to 32 interrupts.
Page 526: Table 18-1. Interrupt Assignments
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.1.1 VIC Interrupt Listing Table 18-1 lists the 32 interrupt source lines for the VIC and their permanent position assignment. For a detailed description of each interrupt, see the chapter for the peripheral that generates the interrupt Table 18-1.
Page 527: Vectored Interrupts
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.1.2 Vectored Interrupts Each interrupt source line must be identified as either an IRQ type or an FIQ type using the Interrupt Select Register (INTSELECT). FIQ interrupts are non-vectored. Once the VIC causes the FIQ interrupt to be asserted to the core, the FIQ interrupt handler is entered directly by loading the instruction at 0x1C independently of the VIC.
Page 528: Clearing Interrupts
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.1.4 Clearing Interrupts The general procedure for clearing an interrupts is: The interrupt must be cleared at its source, regardless of whether the interrupt source is external, internal, or software generated. The interrupt must be cleared within the VIC by writing any value to the VECTADDRx register.
Page 529: Table 18-2. Vic Register Summary
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2 Register Reference This section provides the VIC register memory mapping and bit fields. 18.2.1 Memory Map Table shows the mapping of the VIC registers. The base address for the VIC is 0xFFFFF000. Table 18-2. VIC Register Summary...
Page 530: Table 18-3. Irqstatus Register
Vectored Interrupt Controller LH79524/LH79525 User’s Guide Table 18-2. VIC Register Summary (Cont’d) ADDRESS OFFSET NAME DESCRIPTION 0x220 VECTCTRL8 Vector Control 8 Register 0x224 VECTCTRL9 Vector Control 9 Register 0x228 VECTCTR10 Vector Control 10 Register 0x22C VECTCTRL11 Vector Control 11 Register...
Page 531: Table 18-5. Fiqstatus Register
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2.2.2 FIQ Status Register (FIQSTATUS) This Read Only register provides the status of the interrupts after FIQ masking. Bits [31:0] correspond to the interrupt number in Table 18-1. Table 18-5. FIQSTATUS Register FIELD FIQStatus...
Page 532: Table 18-9. Intselect Register
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.2.2.4 Interrupt Select Register (INTSELECT) This register selects whether the corresponding interrupt source generates an FIQ or an IRQ interrupt. Bits [31:0] correspond to the interrupt number in Table 18-1 Table 18-9. INTSELECT Register...
Page 533: Table 18-13. Intenclear Register
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2.2.6 Interrupt Enable Clear Register (INTENCLEAR) This register clears the individual bits in the INTENABLE Register. Bits [31:0] correspond to the interrupt number in Table 18-1. Table 18-13. INTENCLEAR Register FIELD IntEnable Clear RESET...
Page 534: Table 18-15. Softint Register
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.2.2.7 Software Interrupt Register (SOFTINT) SoftInt is the Software Interrupt Register. This register generates software interrupts. Bits [31:0] correspond to the interrupt number in Table 18-1. Note that interrupt number 1 is the only inter- rupt souce not associated with a physical hardware interrrupt and is therefore reserved for soft- ware interrupts.
Page 535: Table 18-17. Softintclear Register
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2.2.8 Software Interrupt Clear Register (SOFTINTCLEAR) This Write Only register clears the corresponding bit (and the interrupt assertion) in the SOFTINT Register. Bits [31:0] correspond to the interrupt number in Table 18-1 Table 18-17. SOFTINTCLEAR Register...
Page 536: Table 18-19. Vectaddr Register
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.2.2.9 Vector Address Register (VECTADDR) The Vector Address Register contains the ISR address of the currently active interrupt. Reading this register provides the address of the ISR, and indicates to the priority hard- ware that the interrupt is being serviced. Writing to this register indicates to the priority hardware that the interrupt has been serviced.
Page 537: Table 18-23. Vectaddrx Registers
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2.2.11 Vector Address Registers (VECTADDRx) There are 16 Vector Address Registers, designated VectAddr0 through VectAddr15. Each register contains the ISR vector addresses for that particular vectored IRQ interrupt. Table 18-23. VECTADDRx Registers FIELD VICVectorAddr...
Page 538: Table 18-25. Vectctrlx Registers
Vectored Interrupt Controller LH79524/LH79525 User’s Guide 18.2.2.12 Vector Control Registers (VECTCTRLx) There are 16 Vector Control Registers, designated VECTCTRL0 through VECTCTRL15. Software uses these registers to assign the desired interrupt to the desired interrupt vector. The interrupt number from Table 18-1 (in hexadecimal) is programmed to the IntSource bits, and the ‘E’...
Page 539: Table 18-27. Itop Register
LH79524/LH79525 User’s Guide Vectored Interrupt Controller 18.2.2.13 Interrupt Test Output Register (ITOP) Reading the ITOP register returns the status of the IRQ and FIQ interrupt request outputs from the VIC to the ARM exception-handling circuitry. Table 18-27. ITOP Register FIELD...
Page 540: Theory Of Operation
When first enabled or when reset, the WDT begins counting from the programmed timing value. The WDT is enabled by programming the CTL:EN bit to 1. The WDT block diagram is shown in Figure 19-1. All descriptions apply to both the LH79524 and LH79525. Version 1.0...
Page 541: Figure 19-1. Watchdog Timer Block Diagram
Watchdog Timer LH79524/LH79525 User’s Guide RESET, CLOCK WDT TIMEOUT RESET GENERATION AND POWER CONTROL (RCPC) PCLK VECTORED nWDINT INTERRUPT CONTROLLER (VIC) WATCHDOG TIMER (WDT) ADVANCED ADVANCED HIGH-PERFORMANCE PERIPHERAL BUS (AHB) BUS (APB) LH79525-38 Figure 19-1. Watchdog Timer Block Diagram 19-2...
Page 542: Wdt Operation Details
LH79524/LH79525 User’s Guide Watchdog Timer 19.1.1 WDT Operation Details The WDT is enabled and disabled by programming the CTL:EN bit to 1. To reset the WDT, program the Reset register (RST) with the value 0x1984. To prevent the WDT from being inadvertently disabled, the Enable function can be locked by setting the CTL Freeze field (CTL:FRZ).
Page 543: Table 19-1. Watchdog Timer Memory Map
Watchdog Timer LH79524/LH79525 User’s Guide 19.2 Register Reference This section describes the location and programming of the WDT registers. 19.2.1 Memory Map Register offsets in Table 19-1 are relative to the Timer base address 0xFFFC3000 Table 19-1. Watchdog Timer Memory Map...
Page 544: Table 19-2. Ctl Register
LH79524/LH79525 User’s Guide Watchdog Timer 19.2.2 Register Descriptions 19.2.2.1 Control Register (CTL) The WDT control register, described in Table 19-2 and Table 19-3 enables and disables the WDT, and specifies the timeout period and interrupt response. Table 19-2. CTL Register...
Page 545: Table 19-4. Rst Description
Watchdog Timer LH79524/LH79525 User’s Guide 19.2.2.2 Counter Reset Register (RST) Write this register to reset the WDT, preventing a timeout. Table 19-4. RST Description FIELD RESET TYPE FIELD RESET undefined TYPE ADDR 0xFFFE3000 + 0x04 Table 19-5. RST Field NAME...
Page 546: Table 19-6. Status Description
LH79524/LH79525 User’s Guide Watchdog Timer 19.2.2.3 Status Register (STATUS) This register, described in Table 19-6 and Table 19-7, provides the status of the WDT interrupts, and allows programming whether a system reset is generated upon the first timeout, or if an interrupt is generated on the first timeout, followed by a system reset if that interrupt is not serviced before a second timeout occurs.
Page 547: Table 19-8. Countx Description
Watchdog Timer LH79524/LH79525 User’s Guide 19.2.2.4 Current Watchdog Count Registers (COUNT[3:0]) The COUNTx registers, described in Table 19-8 and Table 19-9, are a set of registers operating as a cascaded counter, reporting the current WDT decrementing value: • COUNT3 contains bits 31 through 24 of the current value •...
Page 548 Advanced Peripheral Bus. Defined in the AMBA specification, the APB connects the lower- performance peripheral blocks. In the LH79524/LH79525, the APB connects a number of peripherals that do not require the speed or bandwidth of the AHB. The APB connects to the AHB via the APB Bridge.
Page 549 This is the access method used by Ethernet. See also MAC and Back Off Time. Direct Memory Access. The LH79524/LH79525 includes an on-chip DMA Controller. 20-2...
Page 550 An ED includes a Transfer Descriptor pointer. Embedded SRAM In the LH79524/LH79525, 16KB of on-chip SRAM. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in SDRAM for dual panel or large displays. The core and DMA controller share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer.
Page 551 LH79524/LH79525 User’s Guide Half Word In the 32-bit LH79524/LH79525, a 16-bit data element structured as an ordered pair of bytes. Half words in this User’s Guide are shown with the most significant byte on the left (or top) and the least significant byte on the right (or bottom). Also see Byte, Nibble, and Word.
Page 552 Most significant word of an ordered sequence. Nibble In the LH79524/LH79525, a 4-bit data element. Nibbles in this User’s Guide are shown with the most significant bit on the left (or top) and the least significant bit on the right (or bottom).
Page 553 Glossary LH79524/LH79525 User’s Guide PHY (Physical Layer Device) Physical Layer Device. The name used for a transceiver in Fast Ethernet systems, which is connected to an electronic device. Pixel Picture Element. The smallest controllable unit of a matrix LCD display.
Page 554 Write Only. Write Only fields should not be read as the data is invalid. Word In the 32-bit LH79524/LH79525, a 32-bit data element structured as an ordered sequence. Words in this User’s Guide are shown with the most significant byte on the left (or top) and the least significant byte on the right (or bottom).
Page 555 SHARP Corporation SHARP Microelectronics of the Americas SHARP Microelectronics Europe Electronic Components & Devices 5700 NW Pacific Rim Blvd. Division of Sharp Electronics (Europe) GmbH 22-22 Nagaike-cho, Abeno-Ku Camas, WA 98607, U.S.A. Sonninstrasse 3 Osaka 545-8522, Japan Phone: (1) 360-834-2500...

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