Table 13-40. Adcpre Register; Table 13-41. Adcpre Fields; Table 13-42. Adcpre Register Values; Adc Clock Prescaler Register (Adcpre) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

13.2.2.17 ADC Clock Prescaler Register (ADCPRE)

The value in this register is used as a divisor for the Source Clock to derive the ADC
clock (ADCCLK) frequency. The ACD clock source (System Clock Oscillator, or HCLK) is
selected with the PCLKSEL1:ADC bit (see Section 13.2.2.13). Following reset, the pres-
caler is programmed to pass the clock through without division. Table 13-42 shows the
valid combinations for ADCDIV and the resulting ADC clock frequency. All other ADCDIV
values are invalid.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0

Table 13-40. ADCPRE Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
///
0 0 0 0
RO RO RO RO RO

Table 13-41. ADCPRE Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
ADC Clock Divisor Program with the clock source divisor for the ADC Clock
ADCDIV
prescaler (see Table 13-42).

Table 13-42. ADCPRE Register Values

ADCDIV
0b00000000 (default)
0b00000001
0b00000010
0b00000100
0b00001000
0b00010000
0b00100000
0b01000000
0b10000000
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFE2000 + 0x48
DESCRIPTION
DIVISOR
1
2
4
8
16
32
64
128
256
Version 1.0
Reset, Clock, and Power Controller
22 21 20 19
0 0 0 0
RO RO RO RO
6 5 4 3
ADCDIV
0 0 0 0
RW RW RW RW
ƒ(ADCCLK)
ƒ(clock source)
ƒ(clock source)/2
ƒ(clock source)/4
ƒ(clock source)/8
ƒ(clock source)/16
ƒ(clock source)/32
ƒ(clock source)/64
ƒ(clock source)/128
ƒ(clock source)/256
18 17 16
0 0 0
RO RO RO
2 1 0
0 0 0
RW RW RW
13-27