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LH79524/LH79252 User's Guide
Chapter 14 - Synchronous Serial Port
14.1 Theory of Operation ..................................................................................... 14-1
14.2 Register Reference ...................................................................................... 14-9
13.2.2.4 Software Reset Register (SOFTRESET)...................................... 13-14
13.2.2.5 Reset Status Register (RSTSTATUS).......................................... 13-15
13.2.2.6 Reset Status Clear Register (RSTSTATUSCLR) ......................... 13-16
13.2.2.7 System Clock Prescaler Register (SYSCLKPRE) ........................ 13-17
13.2.2.8 CPU Clock Prescaler Register (CPUCLKPRE) ............................ 13-18
13.2.2.9 Peripheral Clock Control Register 0 (PCLKCTRL0) ..................... 13-19
13.2.2.10 Peripheral Clock Control Register 1 (PCLKCTRL1) ................... 13-20
13.2.2.11 AHB Clock Control Register (AHBCLKCTRL) ............................ 13-21
13.2.2.12 Peripheral Clock Select Register 0 (PCLKSEL0) ....................... 13-22
13.2.2.13 Peripheral Clock Select Register 1 (PCLKSEL1) ....................... 13-23
13.2.2.14 Silicon Revision Register (SILICONREV)................................... 13-24
13.2.2.15 LCD Clock Prescaler Register (LCDPRE).................................. 13-25
13.2.2.16 SSP Clock Prescaler Register (SSPPRE).................................. 13-26
13.2.2.17 ADC Clock Prescaler Register (ADCPRE) ................................. 13-27
13.2.2.18 USB Clock Prescaler Register (USBPRE) ................................. 13-28
13.2.2.19 External Interrupt Configuration Register (INTCONFIG) ............ 13-29
13.2.2.20 External Interrupt Clear Register (INTCLR)................................ 13-31
13.2.2.21 Core Clock Configuration Register (CORECONFIG) ................. 13-32
13.2.2.22 System PLL Control Register (SYSPLLCTL) ............................. 13-33
13.2.2.23 USB PLL Control Register (USBPLLCTL).................................. 13-34
14.1.1 Timing Waveforms ................................................................................ 14-3
14.1.2 Motorola SPI Frame Format .................................................................. 14-4
14.1.3 Texas Instruments Frame Format ......................................................... 14-5
14.1.4 National Semiconductor Frame Format ................................................ 14-6
14.1.5 Clock Generation................................................................................... 14-7
14.1.6 Interrupts ............................................................................................... 14-7
14.1.6.1 Receive Interrupt ............................................................................ 14-7
14.1.6.2 Transmit Interrupt ........................................................................... 14-8
14.1.6.3 Receive Overrun Interrupt .............................................................. 14-8
14.1.6.4 Receive Timeout Interrupt .............................................................. 14-8
14.1.6.5 SSPINTR ........................................................................................ 14-8
14.2.1 Memory Map ......................................................................................... 14-9
14.2.2 Register Descriptions .......................................................................... 14-10
14.2.2.1 Control Register 0 (CTRL0).......................................................... 14-10
14.2.2.2 Control Register 1 (CTRL1).......................................................... 14-12
14.2.2.3 Data Register - Receive/Transmit FIFO Register (DR)............... 14-13
14.2.2.4 Status Register (SR)..................................................................... 14-14
14.2.2.5 Clock Prescale Register (CPSR).................................................. 14-15
14.2.2.6 Interrupt Mask Set and Clear Register (IMSC)............................. 14-16
14.2.2.7 Raw Interrupt Status Register (RIS) ............................................. 14-17
14.2.2.8 Masked Interrupt Status Register (MIS) ....................................... 14-18
14.2.2.9 Interrupt Clear Register (ICR)....................................................... 14-19
14.2.2.10 DMA Control Register (DCR) ..................................................... 14-20
Version 1.0
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