Table 7-43. Dynamictmrd Register; Table 7-44. Dynamictmrd Fields; Dynamic Memory Load Mode Register To Active Command Time Register (Dynamictmrd) - Sharp LH79524 User Manual

External Memory Controller
7.5.2.17 Dynamic Memory Load Mode Register to
Active Command Time Register (DYNAMICTMRD)
The Dynamic Memory Load Mode Register to Active Command Time Register specifies
the Load Mode Register to Active Command Time, tMRD. This value is normally found in
SDRAM data sheets as tMRD, or tRSA.
These registers must only be modified during system initialization, or when there are
no current or outstanding transactions. Software can ensure that there are no current or
outstanding transactions by waiting until the memory controller is idle, then entering
Low-Power Mode (CONTROL:MODE = 1), or Disable Mode (CONTROL:ENABLE = 0).
When in these two modes, external memory access is not allowed, ensuring that
changing parameters will not corrupt external data. Low-Power Mode automatically
refreshes SDRAM; Disable Mode requires commanding the SDRAM to Self Refresh
(DYNMCTRL:SR = 1) prior to entering Disable.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
7-46

Table 7-43. DYNAMICTMRD Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 7-44. DYNAMICTMRD Fields

BITS NAME
31:4 /// Reserved Reading returns 0. Write the reset value.
Load Mode Register to Active Command Time
3:0 tMRD
Time = (tMRD + 1) External Memory Clock periods
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFF1000 + 0x058
FUNCTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 1 1
RO RO RO RW RW
17 16
0 0
RO RO
1 0
tMRD
1 1
RW RW