Table 15-16. Capn Register; Table 15-17. Capn Register Definitions; Timer 0 Capture Registers (Capn) - Sharp LH79524 User Manual

Timers

15.2.2.7 Timer 0 Capture Registers (CAPn)

There are five CAPn Registers for Timer 0. They are designated:
• CAPA
• CAPB
• CAPC
• CAPD
• CAPE
Each register is a 16-bit, Read Only register. When a capture condition occurs, the con-
tents of the counter CNT0 are stored into the associated Capture Register. Capture Reg-
isters correspond to the input signals CTCAP0A through CTCAP0E, respectively. The
edge of the input signal used to trigger the capturing operation is selected with the
CMP_CAP_CTRL Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0
15-14

Table 15-16. CAPn Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO

Table 15-17. CAPn Register Definitions

NAME
Reserved Reading this field returns 0. Write the reset value.
///
CAPTURE0 Timer 0 Capture Register 16-bit capture register value.
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
CAPTURE0
0 0 0 0
RO RO RO RO
CAPA: 0xFFFC4000 + 0x1C
CAPB: 0xFFFC4000 + 0x20
CAPC: 0xFFFC4000 + 0x24
CAPD: 0xFFFC4000 + 0x28
CAPE: 0xFFFC4000 + 0x2C
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RO RO