Table 18-9. Intselect Register; Table 18-10. Intselect Fields; Table 18-11. Intenable Register; Table 18-12. Intenable Fields - Sharp LH79524 User Manual

Vectored Interrupt Controller

18.2.2.4 Interrupt Select Register (INTSELECT)

This register selects whether the corresponding interrupt source generates an FIQ or an
IRQ interrupt. Bits [31:0] correspond to the interrupt number in Table 18-1
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0 IntSelect
18.2.2.5 Interrupt Enable Register (INTENABLE)
The bits in this register allow software to individually enable and disable interrupts. Bits
[31:0] correspond to the interrupt number in Table 18-1
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:0 IntEnable
18-8

Table 18-9. INTSELECT Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 18-10. INTSELECT Fields

NAME
Interrupt Type Selects the type of interrupt for the interrupt request.
For each bit:
1 = FIQ interrupt
0 = IRQ interrupt

Table 18-11. INTENABLE Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 18-12. INTENABLE Fields

NAME
Interrupt Enable Following a System Reset, all interrupts are disabled.
Read, for each bit:
1 = Interrupt is enabled, allowing interrupt request to the core CPU
0 = Interrupt is disabled
Write, for each bit:
1 = Enable the corresponding interrupt
0 = Has no effect
26 25 24 23
IntSelect
0 0 0 0
RW RW RW RW
10 9 8 7
IntSelect
0 0 0 0
RW RW RW RW
0x00C
0xFFFFF000 +
DESCRIPTION
26 25 24 23
IntEnable
0 0 0 0
RW RW RW RW
10 9 8 7
IntEnable
0 0 0 0
RW RW RW RW
0x010
0xFFFFF000 +
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
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22 21 20 19 18
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
.
22 21 20 19 18
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
RW RW
1 0
0 0
RW RW
17 16
0 0
RW RW
1 0
0 0
RW RW