Operational Overview - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

6.1.1 Operational Overview

The Ethernet Receive Block and Ethernet Transmit Block contain the logic to implement
receive and transmit operations at either 10 Mbits/s or 100 Mbits/s. These two blocks
implement a Media Independent Interface (MII) for High Speed Ethernet, and Attachment
Unit Interface (AUI) for 10 Mbits/s Ethernet (throughout the rest of the document, 'MII' will
be used to mean both MII and AUI). The MII allows seamless connection to Physical Layer
devices (PHYs).
The Receive and Transmit Blocks can operate independently of one another, thus allowing
the EMAC to provide both half-duplex and full-duplex operation. During half-duplex oper-
ation, the EMAC can be programmed so that any frame received while the EMAC is trans-
mitting is discarded. Flow control during reception is handled by transmitting null frames to
intentionally cause collisions.
The Receive and Transmit Blocks also handle error checking, collision detection,
carrier sense, and CRC/FCS generation and decoding. Full CSMA/CD protocol is imple-
mented. Error frames are automatically discarded without being written to the system
memory buffers.
Up to four MAC addresses can be programmed into the EMAC. The MAC address(es)
must be stored in non-volatile memory off-chip, and read by software upon initiatlization.
Software programs the MAC address(es) into the Address Specific register(s), and also
must use it to build transmit frames.
Incoming packets are checked for error and validity in the Receive Block. Then, the
Address Checking Block compares addresses of received packets to the addresses stored
in the Specific Address Registers, and upon match, copies the packet to the receive buffer.
Transmit frame data is assembled by software in buffers, which are then retrieved,
checked for validity, and transmitted over the Ethernet connection.
Receive and transmit data is stored in buffers allocated in areas in system memory defined
by software. The EMAC maintains a pointer to these buffers and automatically handles
pointer indexing. The onboard DMA Interface is an AHB master, and can directly read and
write data in system memory, allowing data handling fast enough to support High Speed
Ethernet at 100 Mbits/s. Clocking is handled by onboard synchronization circuits, and the
divisor is programmable to allow a wide range of HCLK frequencies.
The Statistics and Control Registers are accessed by the core via the APB, through the
Register Interface. The Statistics Registers log a wide range of network statistics for use
by the LH79524/LH79525 software, RMON/MIB, or other uses. The control registers allow
software to define network parameters, enable and disable the Receive and Transmit
Blocks, enable and disable interrupts, view status information, and also implement the
MDIO interface to manage the PHY.
Version 1.0
Ethernet MAC Controller
6-3