Page 1 LH75400/01/10/11 System-on-Chip Preliminary User’s Guide 7/15/03...
Page 2 Suggested applications (if any) are for standard use; See Important Restrictions for limitations on spe- cial applications. See Limited Warranty for Sharp’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRAN- TIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FIT- NESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED.
Page 3: Table Of Contents
Table of Contents Preface Supplemental Documentation ................xxxi Terms and Conventions ..................xxxi Multiplexed Pins ....................xxxi Pin Names ......................xxxii Peripheral Devices ................... xxxii Register Names....................xxxii Register Addresses ..................xxxii Register Tables ....................xxxiii Chapter 1 – Introduction 1.1 Product Overview .....................
Page 4 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide Chapter 4 – LH75400 SoC 4.1 LH75400 Features.................... 4-1 4.2 LH75400 Block Diagram .................. 4-2 4.3 LH75400 Applications ..................4-3 4.4 LH75400 Pin Diagram ..................4-4 4.5 LH75400 Numerical Pin Listing ................ 4-5 4.6 LH75400 Signal Descriptions ................
Page 5 LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents 9.3.1 RCPC Register Summary ................. 9-6 9.3.2 RCPC Register Definitions ................ 9-7 9.3.2.1 Control Register.................. 9-7 9.3.2.2 Identification Register ................. 9-8 9.3.2.3 Remap Control Register ..............9-8 9.3.2.4 Soft Reset Register ................9-9 9.3.2.5 Reset Status Register...............
Page 6 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide Chapter 11 – I/O Configuration 11.1 IOCON Theory of Operation................. 11-1 11.2 IOCON Programmer’s Model ............... 11-2 11.2.1 IOCON Register Summary ..............11-2 11.2.2 IOCON Register Definitions ..............11-3 11.2.2.1 EBI Interface Muxing Register............11-3 11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register ........
Page 7 LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents 13.3.2.1 Horizontal Timing Panel Control Register ........13-11 13.3.2.2 Horizontal Timing Restrictions............13-12 13.3.2.3 Vertical Timing Panel Control Register......... 13-13 13.3.2.4 Clock and Signal Polarity Control Register........13-14 13.3.2.5 Upper Panel Frame Buffer Base Address Register...... 13-15 13.3.2.6 Lower Panel Frame Buffer Base Address Register......
Page 8 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.3 Vertical Timing Panel Control Register......... 14-10 14.3.2.4 Clock and Signal Polarity Control Register........14-11 14.3.2.5 Upper Panel Frame Buffer Base Address Register...... 14-12 14.3.2.6 Lower Panel Frame Buffer Base Address Register...... 14-13 14.3.2.7 Interrupt Enable Register..............
Page 9 LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents Chapter 16 – Watchdog Timer 16.1 WDT Features ....................16-1 16.2 WDT Theory of Operation ................16-2 16.3 WDT Programmer’s Model................16-2 16.3.0.1 WDT Register Summary..............16-2 16.3.1 WDT Register Definitions ..............16-3 16.3.1.1 Control Register................
Page 10 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide 18.5.3 SSP Interrupts ..................18-19 18.5.3.1 Receive Interrupt ................18-19 18.5.3.2 Transmit Interrupt ................. 18-19 18.5.3.3 Receive Overrun Interrupt ............18-19 18.5.3.4 Receive Timeout Interrupt ............18-20 18.5.3.5 SSPINTR ..................18-20 Chapter 19 – UART0 and UART1 19.1 UART0 and UART1 Features...............
Page 11 LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents 20.3.1.2 Register Bank 1 ................20-8 20.3.1.3 Register Bank 2 ................20-8 20.3.1.4 Register Bank 3 ................20-9 20.3.2 UART2 Register Definitions ..............20-10 20.3.2.1 Transmit Buffered Data Register ..........20-10 20.3.2.2 Receive Buffered Data Register ........... 20-11 20.3.2.3 BRGA Divisor Least Significant Byte Register ......
Page 12 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.3 Port A Data Direction Register ............21-6 21.2.3.4 Port B Data Direction Register ............21-7 21.2.3.5 Port C Data Register ..............21-8 21.2.3.6 Port D Data Register ..............21-9 21.2.3.7 Port C Data Direction Register ............. 21-10 21.2.3.8 Port D Data Direction Register .............
Page 13 LH75400/01/10/11 (Preliminary) User’s Guide Table of Contents 22.3.2.13 Transmit Buffer ................22-23 22.3.2.14 Transmit Buffer Descriptor Field..........22-24 22.3.2.15 CAN Receive Buffer ..............22-26 22.3.2.16 Receive Buffer Descriptor Field..........22-27 22.3.2.17 Acceptance Code Registers ............22-27 22.3.2.18 Acceptance Mask Registers (AMR0 - AMR3) ......22-27 22.3.2.19 Receive Message Counter Register...........
Page 14 Table of Contents LH75400/01/10/11 (Preliminary) User’s Guide Chapter 25 – Recommended Layout Practices 25.1 Protecting Against ElectroStatic Discharge..........25-1 25.1.1 Special ESD Considerations ..............25-1 25.2 Printed Circuit Board Layout Practices............25-2 25.2.1 Power Supply Decoupling ..............25-2 25.2.2 Required VDDA_PLL, VSSA_PLL Filter ..........25-2 25.2.3 Unused Input Signal Conditioning ............
Page 15 List of Figures Preface Figure 1. Multiplexer....................xxxiv Figure 2. Register with Bit Field Named..............xxxiv Figure 3. Register with Multiple Bit Fields Named............ xxxv Figure 4. Register with Bit Field Named..............xxxv Chapter 1 – Introduction Figure 1-1. Crystal Oscillator..................1-7 Chapter 2 –...
Page 16 List of Figures LH75400/01/10/11 (Preliminary) User’s Guide Chapter 13 – Color Liquid Crystal Display Controller Figure 13-1. Color LCD Controller Block Diagram (LH75401 and LH75411 Only) .. 13-2 Figure 13-2. STN Horizontal Timing Diagram ............13-31 Figure 13-3. STN Vertical Timing Diagram ............13-32 Figure 13-4.
Page 17 LH75400/01/10/11 (Preliminary) User’s Guide List of Figures Chapter 22 – Controller Area Network Figure 22-1. CAN Controller Block Diagram ............22-1 Figure 22-2. General Structure of a Bit Period ............22-15 Chapter 23 – Analog-to-Digital Converter/Brownout Detector Figure 23-1. ADC Block Diagram ................23-2 Figure 23-2.
Page 18 List of Tables Preface Table 1. Register Name ..................xxxiii Table 2. Bit Definitions .................... xxxiii Chapter 1 – Introduction Table 1-1. Feature Summary ..................1-1 Table 1-2. Bus Master Priority..................1-2 Table 1-3. Device Operating Modes................1-3 Table 1-4. Linear Regulator Ramp-up Time............... 1-5 Chapter 2 –...
Page 19 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Table 7-15. BCR2 Register Definitions ..............7-17 Table 7-16. BCR3 Register ..................7-19 Table 7-17. BCR3 Register Definitions ..............7-19 Table 7-18. SMC System Reset Default Memory Width .......... 7-21 Chapter 9 – Reset, Clock, and Power Controller Table 9-1.
Page 20 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Table 10-9. IntSelect Register................10-12 Table 10-10. IntSelect Register Definitions ............10-12 Table 10-11. IntEnable Register................10-13 Table 10-12. IntEnable Register Definitions............10-13 Table 10-13. IntEnClear Register................10-14 Table 10-14. IntEnClear Register Definitions ............10-14 Table 10-15.
Page 21 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Chapter 12 – Direct Memory Access Controller Table 12-1. DMA Controller Stream Assignments and Request Priority....12-1 Table 12-2. DMA Register Summary ............... 12-7 Table 12-3. Data Stream Register Summary ............12-7 Table 12-4. CTRL Register ..................12-9 Table 12-5.
Page 22 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Table 13-33. Palette Register Use for TFT and STN ..........13-23 Table 13-34. HRTFTC Register Summary ............. 13-25 Table 13-35. Setup Register .................. 13-26 Table 13-36. Setup Register Definitions..............13-26 Table 13-37. CTRL Register .................. 13-27 Table 13-38.
Page 23 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Chapter 15 – Timers Table 15-1. Timer 0 Register Summary ..............15-9 Table 15-2. Timer 1 Register Summary ..............15-9 Table 15-3. Timer 2 Register Summary ..............15-9 Table 15-4. CTRL Register ..................15-10 Table 15-5.
Page 24 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Chapter 16 – Watchdog Timer Table 16-1. WDT Register Summary ............... 16-2 Table 16-2. CTRL Register ..................16-3 Table 16-3. CTRL Register Definitions..............16-3 Table 16-4. CNTR Register..................16-4 Table 16-5. CNTR Register Definitions ..............16-4 Table 16-6.
Page 25 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Table 18-10. SR Register Definitions ..............18-15 Table 18-11. CPSR Register.................. 18-16 Table 18-12. CPSR Register Definitions ..............18-16 Table 18-13. IIR/ICR Register (Read Characteristic) ..........18-17 Table 18-14. IIR/ICR Register Definitions (Read Operation) ......... 18-17 Table 18-17.
Page 26 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Chapter 20 – UART2 Table 20-1. Register Bank 0 (Default On Reset)............20-7 Table 20-2. Register Bank 1..................20-8 Table 20-3. Register Bank 2..................20-8 Table 20-4. Register Bank 3..................20-9 Table 20-5. TXD Register..................20-10 Table 20-6.
Page 27 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Table 20-47. ICM Register ..................20-30 Table 20-48. ICM Register Definitions ..............20-30 Table 20-49. GSR Register ..................20-31 Table 20-50. GSR Register Definitions ..............20-31 Table 20-51. FMD Register ..................20-32 Table 20-52. FMD Register Definitions ..............20-32 Table 20-53.
Page 28 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Table 21-18. PDDDR Register Definitions ............. 21-11 Table 21-19. PEDR Register.................. 21-12 Table 21-20. PEDR Register Definitions ..............21-12 Table 21-21. PFDR Register .................. 21-13 Table 21-22. PFDR Register Definitions ..............21-13 Table 21-23. PEDDR Register ................21-14 Table 21-24.
Page 29 List of Tables LH75400/01/10/11 (Preliminary) User’s Guide Table 22-24. EWLR Register Definitions..............22-20 Table 22-25. RXERR Register ................22-21 Table 22-26. RXERR Register Definitions ............. 22-21 Table 22-27. CAN Transmit Buffer ................. 22-23 Table 22-28. Transmit Frame (SFF)............... 22-24 Table 22-29. Transmit Frame (EFF)............... 22-24 Table 22-30.
Page 30 LH75400/01/10/11 (Preliminary) User’s Guide List of Tables Table 23-28. MIS Register Definitions..............23-24 Table 23-29. IC Register ..................23-25 Table 23-30. IC Register Definitions ..............23-25 Chapter 24 – LCD Pin Multiplexing Table 24-1. LCD Panel Signal Multiplexing.............. 24-1 Table 24-2. LCD External Pin Multiplexing (LH75401 and LH75411) ...... 24-2 Table 24-3.
Page 31: Preface
This User’s Guide is the principal technical reference for these SoCs. It is intended for engineers responsible for designing, integrating, programming, and testing embedded systems based on these four SHARP SoCs. Electrical Characteristics are found in the Data Sheet. This User’s Guide assumes that the reader: •...
Page 32: Pin Names
Preface LH75400/01/10/11 (Preliminary) User’s Guide Pin Names Package pins are named to indicate the signal(s) or functionality available at the pin. If the signal or function is active LOW, the name is prefixed with a lower-case ‘n’, such as nCS2. Multiplexed pins are named to indicate all available functions, such as Pin 30: PB0/nCS1.
Page 33: Register Tables
LH75400/01/10/11 (Preliminary) User’s Guide Preface Register Tables All registers are presented in tabular format. A primary table presents each register’s name, address, permissions, bit-field names, and the register’s contents at reset. Subse- quent tables detail the specific function(s) of all bit fields in the register and explain any important variations that may exist.
Page 34: Figure 1. Multiplexer
Preface LH75400/01/10/11 (Preliminary) User’s Guide Block Diagrams The functional descriptions in this User’s Guide include block diagrams with symbols rep- resenting logical or mathematical operations or selections, usually the result of writing a value to a register. Figure 1 shows an example of a multiplexer with three inputs and one output (the result).
Page 35: Figure 3. Register With Multiple Bit Fields Named
LH75400/01/10/11 (Preliminary) User’s Guide Preface Figure 3 is similar to Figure 2, except that Figure 3 references multiple (different) BITFIELDS in the REGISTERNAME register. REGISTERNAME: [BITFIELDNAME, BITFIELDNAME] INPUT f ( ) OUTPUT LH754xx-85 Figure 3. Register with Multiple Bit Fields Named Not all bit fields are named.
Page 36: Product Overview
Chapter 1 Introduction 1.1 Product Overview LH75400/01/10/11 is a family of four 16/32-bit System-on-Chip (SoC) devices: • LH75401 — contains the superset of features. See Chapter 2. • LH75411 — similar to the LH75401, without the Controller Area Network (CAN) 2.0B interface.
Page 37: Arm And Thumb State
Introduction LH75400/01/10/11 (Preliminary) User’s Guide 1.2 ARM and Thumb State These SoCs consist of a 32-bit core processor with a 16-bit data bus that can operate in ARM Thumb mode for executing 16-bit instructions. Thumb is an extension to the ARM architecture.
Page 38: Operating Modes
LH75400/01/10/11 (Preliminary) User’s Guide Introduction An APB bridge is used to provide access to the various APB peripherals: • Analog-to-Digital Converter • Controller Area Network (LH75401 and LH75400 only) • Counter/Timers • General Purpose Input/Output • I/O Configuration • Real Time Clock •...
Page 39: Normal Mode
Introduction LH75400/01/10/11 (Preliminary) User’s Guide 1.4.1 Normal Mode As its name implies, Normal Mode is the mode in which the SoC is placed for normal oper- ation. The system clock is generated from the PLL. In this mode, the JTAG interface is active and accesses the boundary scan TAP Controller.
Page 40: Linear Regulator Power
LH75400/01/10/11 (Preliminary) User’s Guide Introduction 1.5.1 Linear Regulator Power When the linear regulator is enabled, the 1.8 V power pins (VDDC) are outputs of the reg- ulator. This allows regulator operation to be verified. An external low ESR capacitor must be tied to the regulator output for stability.
Page 41: Real-World Component Selection
Introduction LH75400/01/10/11 (Preliminary) User’s Guide The power (VDDA_PLL) path must be a single wire that runs: • From the IC package pin to the high-frequency capacitor • Then to the low-frequency capacitor • Then through the series element (e.g., resistor) •...
Page 42: Crystal Oscillator Usage
LH75400/01/10/11 (Preliminary) User’s Guide Introduction 1.6 Crystal Oscillator Usage When a chip containing a crystal oscillator is used on a board, the user must make some resistance and capacitance connections from the chip to the board. Figure 1-1 shows an application diagram for the crystal oscillator. Rfb is a feedback resistor, and C1 and C2 are load capacitances.
Page 43: Reset Strategy
Introduction LH75400/01/10/11 (Preliminary) User’s Guide The frequency ranges of the PLL and crystal oscillator together make for a crystal frequency range of operation that is from 14 MHz to 20 MHz. However, since the UART clocks are driven by the crystal oscillator, an oscillator frequency of 14.7456 MHz is rec- ommended for this design (but not required).
Page 44: Chapter 2 - Lh75401 Soc
Chapter 2 LH75401 SoC 2.1 LH75401 Features • ARM7TDMI-S™ Core • Up to 70 MHz System Clock (HCLK)* – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz. •...
Page 45: Lh75401 Block Diagram
LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide • JTAG Debug Interface and Boundary Scan • Single 3.3 V Supply • 5.0 V Tolerant Inputs • 144-pin LQFP Package • -40°C to +85°C Operating Temperature. NOTE: *70 MHz Operation requires the use of the internal 3.3 V-to-1.8 V internal linear regulator. 2.2 LH75401 Block Diagram Figure 2-1 shows a block diagram of the LH75401.
Page 46: Lh75401 Applications
LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC 2.3 LH75401 Applications The SHARP LH75401 is ideally suited for a variety of applications, including white-goods and industrial-control. Typical white-goods applications include, but are not limited to: • Air conditioners • Washing machines • Refrigerators •...
Page 47: Lh75401 Pin Diagram
LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide 2.4 LH75401 Pin Diagram TOP VIEW 144-PIN LQFP PF5/CTCAP2A /CTCMP2A PD6/INT6/DREQ PF4/CTCAP1B/CTCMP1B nRESETOUT PF3/CTCAP1A /CTCMP1A LINREGEN PF2/CTCAP0E PF1/CTCAP0D PF0/CTCAP0C RTCK PG7/CTCAP0B/CTCMP0B PG6/CTCAP0A /CTCMP0A TEST1 PG5/CTCLK TEST2 nRESETIN PG4/LCDVEEEN /LCDMOD PG3/LCDVDDEN PG2/LCDDSPLEN /LCDREV PG1/LCDCLS PG0/LCDPS PH7/LCDDCLK PH6/LCDLP/LCDHRLP PH5/LCDFP/LCDSPS...
Page 48: Lh75401 Numerical Pin Listing
LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC 2.5 LH75401 Numerical Pin Listing Table 2-1. LH75401 Numerical Pin List FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional 8 mA Bidirectional Power None 8 mA Bidirectional 8 mA...
Page 49 LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 2-1. LH75401 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional Pull-down Ground None Power None 8 mA Output 8 mA Output 8 mA Output...
Page 50 LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC Table 2-1. LH75401 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET nPOR None Input Pull-up 2, 3 XTAL32IN None Input XTAL32OUT None Output VSSA_PLL Ground None...
Page 51 LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 2-1. LH75401 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET LCDDSPLEN LCDREV 8 mA Bidirectional LCDCLS 8 mA Bidirectional LCDPS 8 mA Bidirectional LCDDCLK 8 mA...
Page 52: Lh75401 Signal Descriptions
LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC 2.6 LH75401 Signal Descriptions Table 2-2. LH75401 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) D[15:0] Input/Output Data Input/Output Signals Output Static Memory Controller Write Enable Output Static Memory Controller Output Enable nWAIT Input Static Memory Controller External Wait Control...
Page 53 LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 2-2. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES COLOR LCD CONTROLLER (CLCDC) LCDMOD Output HR-TFT Signal Used by the Row Driver (HR-TFT only) LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) LCDVDDEN Output Digital Supply Enable...
Page 54 LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC Table 2-2. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES ANALOG-TO-DIGITAL CONVERTER (ADC) AN3 (LR/Y-) AN4 (Wiper) AN2 (LL/Y+) Input ADC Inputs AN1 (UR/X-) AN0 (UL/X+) TIMER 0 CTCAP0[A:E] Input Timer 0 Capture Inputs CTCMP0[A:B] Output Timer 0 Compare Outputs...
Page 55 LH75401 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 2-2. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES Input/Output General Purpose I/O Signals - Port D Input General Purpose I/O Signals - Port J Input/Output General Purpose I/O Signals - Port E Input/Output General Purpose I/O Signals - Port F Input/Output General Purpose I/O Signals - Port G Input/Output General Purpose I/O Signals - Port H...
Page 56 LH75400/01/10/11 (Preliminary) User’s Guide LH75401 SoC Table 2-2. LH75401 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES INT5 Input External Interrupt Input 5 INT4 Input External Interrupt Input 4 INT3 Input External Interrupt Input 3 INT2 Input External Interrupt Input 2 INT1 Input External Interrupt Input 1...
Page 57: Chapter 3 - Lh75411 Soc
Chapter 3 LH75411 SoC 3.1 LH75411 Features • ARM7TDMI-S™ Core • Up to 70 MHz System Clock (HCLK) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz. •...
Page 58: Lh75411 Block Diagram
LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide • Single 3.3 V Supply • 5.0 V Tolerant Inputs • 144-pin LQFP Package • -40°C to +85°C Operating Temperature. 3.2 LH75411 Block Diagram Figure 3-1 shows a block diagram of the LH75411. For information about the blocks shown in this figure, see the appropriate Chapters in this User’s Guide.
Page 59: Lh75411 Applications
LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC 3.3 LH75411 Applications The SHARP LH75411 is ideally suited for a variety of applications, including white-goods and industrial-control. Typical white-goods applications include, but are not limited to: • Air conditioners • Washing machines • Refrigerators •...
Page 60: Lh75411 Pin Diagram
LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide 3.4 LH75411 Pin Diagram TOP VIEW 144-PIN LQFP PF5/CTCAP2A /CTCMP2A PD6/INT6/DREQ PF4/CTCAP1B/CTCMP1B nRESETOUT PF3/CTCAP1A /CTCMP1A LINREGEN PF2/CTCAP0E PF1/CTCAP0D PF0/CTCAP0C RTCK PG7/CTCAP0B/CTCMP0B PG6/CTCAP0A /CTCMP0A TEST1 PG5/CTCLK TEST2 nRESETIN PG4/LCDVEEEN /LCDMOD PG3/LCDVDDEN PG2/LCDDSPLEN /LCDREV PG1/LCDCLS PG0/LCDPS PH7/LCDDCLK PH6/LCDLP/LCDHRLP PH5/LCDFP/LCDSPS...
Page 61: Lh75411 Numerical Pin Listing
LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC 3.5 LH75411 Numerical Pin Listing Table 3-1. LH75411 Numerical Pin List FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional 8 mA Bidirectional Power None 8 mA Bidirectional 8 mA...
Page 62 LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 3-1. LH75411 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional Pull-down Ground None Power None 8 mA Output 8 mA Output 8 mA Output...
Page 63 LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC Table 3-1. LH75411 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET nPOR None Input Pull-up 2, 3 XTAL32IN None Input XTAL32OUT None Output VSSA_PLL Ground None...
Page 64 LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 3-1. LH75411 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET LCDDSPLEN LCDREV 8 mA Bidirectional LCDCLS 8 mA Bidirectional LCDPS 8 mA Bidirectional LCDDCLK 8 mA...
Page 65: Lh75411 Signal Descriptions
LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC 3.6 LH75411 Signal Descriptions Table 3-2. LH75411 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) D[15:0] Input/Output Data Input/Output Signals Output Static Memory Controller Write Enable Output Static Memory Controller Output Enable nWAIT Input Static Memory Controller External Wait Control...
Page 66 LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 3-2. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES COLOR LCD CONTROLLER (CLCDC) LCDMOD Output HR-TFT Signal Used by the Row Driver (HR-TFT only) LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) LCDVDDEN Output Digital Supply Enable...
Page 67 LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC Table 3-2. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES TIMER 0 CTCAP0[A:E] Input Timer 0 Capture Inputs CTCMP0[A:B] Output Timer 0 Compare Outputs CTCLK Input Common External Clock TIMER 1 CTCAP1[A:B] Input Timer 1 Capture Inputs...
Page 68 LH75411 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 3-2. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES Input General Purpose I/O Signals - Port J Input/Output General Purpose I/O Signals - Port E Input/Output General Purpose I/O Signals - Port F Input/Output General Purpose I/O Signals - Port G Input/Output General Purpose I/O Signals - Port H Input/Output General Purpose I/O Signals - Port I...
Page 69 LH75400/01/10/11 (Preliminary) User’s Guide LH75411 SoC Table 3-2. LH75411 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES INT0 Input External Interrupt Input 0 nPOR Input Power-on Reset Input XTAL32IN Input 32.768 kHz Crystal Clock Input XTAL32OUT Output 32.768 kHz Crystal Clock Output XTALIN Input Crystal Clock Input...
Page 70: Chapter 4 - Lh75400 Soc
Chapter 4 LH75400 SoC 4.1 LH75400 Features • ARM7TDMI-S™ Core • Up to 70 MHz System Clock (HCLK) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz. •...
Page 71: Lh75400 Block Diagram
LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide 4.2 LH75400 Block Diagram Figure 4-1 shows a block diagram of the LH75400. For information about the blocks shown in this figure, see the appropriate Chapters in this User’s Guide. LH75400 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER...
Page 72: Lh75400 Applications
LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC 4.3 LH75400 Applications The SHARP LH75400 is ideally suited for a variety of applications, including white-goods and industrial-control. Typical white-goods applications include, but are not limited to: • Air conditioners • Washing machines • Refrigerators •...
Page 73: Lh75400 Pin Diagram
LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide 4.4 LH75400 Pin Diagram TOP VIEW 144-PIN LQFP PF5/CTCAP2A/CTCMP2A PD6/INT6/DREQ PF4/CTCAP1B/CTCMP1B nRESETOUT PF3/CTCAP1A/CTCMP1A LINREGEN PF2/CTCAP0E PF1/CTCAP0D PF0/CTCAP0C RTCK PG7/CTCAP0B/CTCMP0B PG6/CTCAP0A/CTCMP0A TEST1 PG5/CTCLK TEST2 nRESETIN PG4/LCDVEEEN PG3/LCDVDDEN PG2/LCDDSPLEN PH7/LCDDCLK PH6/LCDLP PH5/LCDFP PH4/LCDEN PH3/LCDVD11 PH2/LCDVD10 PH1/LCDVD9 PH0/LCDVD8 PI7/LCDVD7 PI6/LCDVD6...
Page 74: Lh75400 Numerical Pin Listing
LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC 4.5 LH75400 Numerical Pin Listing Table 4-1. LH75400 Numerical Pin List FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional 8 mA Bidirectional Power None 8 mA Bidirectional 8 mA...
Page 75 LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 4-1. LH75400 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional Pull-down Ground None Power None 8 mA Output 8 mA Output 8 mA Output...
Page 76 LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC Table 4-1. LH75400 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET nPOR None Input Pull-up 2, 3 XTAL32IN None Input XTAL32OUT None Output VSSA_PLL Ground None...
Page 77 LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 4-1. LH75400 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET LCDDSPLEN 8 mA Bidirectional 8 mA Bidirectional 8 mA Bidirectional LCDDCLK 8 mA Bidirectional Power None...
Page 78: Lh75400 Signal Descriptions
LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC 4.6 LH75400 Signal Descriptions Table 4-2. LH75400 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) D[15:0] Input/Output Data Input/Output Signals Output Static Memory Controller Write Enable Output Static Memory Controller Output Enable nWAIT Input Static Memory Controller External Wait Control...
Page 79 LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 4-2. LH75400 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES LCD CONTROLLER (LCDC) LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) LCDVDDEN Output Digital Supply Enable LCDDSPLEN Output LCD Panel Power Enable LCDDCLK Output LCD Panel Clock...
Page 80 LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC Table 4-2. LH75400 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES TIMER 0 CTCAP0[A:E] Input Timer 0 Capture Inputs CTCMP0[A:B] Output Timer 0 Compare Outputs CTCLK Input Common External Clock TIMER 1 CTCAP1[A:B] Input Timer 1 Capture Inputs...
Page 81 LH75400 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 4-2. LH75400 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES Input General Purpose I/O Signals - Port J Input/Output General Purpose I/O Signals - Port E Input/Output General Purpose I/O Signals - Port F Input/Output General Purpose I/O Signals - Port G Input/Output General Purpose I/O Signals - Port H Input/Output General Purpose I/O Signals - Port I...
Page 82 LH75400/01/10/11 (Preliminary) User’s Guide LH75400 SoC Table 4-2. LH75400 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES INT0 Input External Interrupt Input 0 nPOR Input Power-on Reset Input XTAL32IN Input 32.768 kHz Crystal Clock Input XTAL32OUT Output 32.768 kHz Crystal Clock Output XTALIN Input Crystal Clock Input...
Page 83: Chapter 5 - Lh75410 Soc
Chapter 5 LH75410 SoC 5.1 LH75410 Features • ARM7TDMI-S™ Core • Up to 70 MHz System Clock (HCLK) – Internal PLL Driven or External Clock Driven – Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz. •...
Page 84: Lh75410 Block Diagram
LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide 5.2 LH75410 Block Diagram Figure 5-1 shows a block diagram of the LH75410. For information about the blocks shown in this figure, see the appropriate Chapters in this User’s Guide. LH75410 14 to 20 MHz 32.768 kHz OSCILLATOR, PLL, POWER...
Page 85: Lh75410 Applications
LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC 5.3 LH75410 Applications The SHARP LH75410 is ideally suited for a variety of applications, including white-goods and industrial-control. Typical white-goods applications include, but are not limited to: • Air conditioners • Washing machines • Refrigerators •...
Page 86: Lh75410 Pin Diagram
LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide 5.4 LH75410 Pin Diagram TOP VIEW 144-PIN LQFP PF5/CTCAP2A/CTCMP2A PD6/INT6/DREQ PF4/CTCAP1B/CTCMP1B nRESETOUT PF3/CTCAP1A/CTCMP1A LINREGEN PF2/CTCAP0E PF1/CTCAP0D PF0/CTCAP0C RTCK PG7/CTCAP0B/CTCMP0B PG6/CTCAP0A/CTCMP0A TEST1 PG5/CTCLK TEST2 nRESETIN PG4/LCDVEEEN PG3/LCDVDDEN PG2/LCDDSPLEN PH7/LCDDCLK PH6/LCDLP PH5/LCDFP PH4/LCDEN PH3/LCDVD11 PH2/LCDVD10 PH1/LCDVD9 PH0/LCDVD8 PI7/LCDVD7 PI6/LCDVD6...
Page 87: Lh75410 Numerical Pin Listing
LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC 5.5 LH75410 Numerical Pin Listing Table 5-1. LH75410 Numerical Pin List FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional 8 mA Bidirectional Power None 8 mA Bidirectional 8 mA...
Page 88 LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 5-1. LH75410 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET 8 mA Bidirectional Pull-down Ground None Power None 8 mA Output 8 mA Output 8 mA Output...
Page 89 LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC Table 5-1. LH75410 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET nPOR None Input Pull-up 2, 3 XTAL32IN None Input XTAL32OUT None Output VSSA_PLL Ground None...
Page 90 LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 5-1. LH75410 Numerical Pin List (Cont’d) FUNCTION FUNCTION FUNCTION FUNCTION OUTPUT BUFFER PULL-UP/PULL-DOWN NOTES AT RESET TYPE DRIVE TYPE AT RESET LCDDSPLEN 8 mA Bidirectional 8 mA Bidirectional 8 mA Bidirectional LCDDCLK 8 mA Bidirectional Power None...
Page 91: Lh75410 Signal Descriptions
LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC 5.6 LH75410 Signal Descriptions Table 5-2. LH75410 Signal Descriptions PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES MEMORY INTERFACE (MI) D[15:0] Input/Output Data Input/Output Signals Output Static Memory Controller Write Enable Output Static Memory Controller Output Enable nWAIT Input Static Memory Controller External Wait Control...
Page 92 LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 5-2. LH75410 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES LCD CONTROLLER (LCDC) LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal) LCDVDDEN Output Digital Supply Enable LCDDSPLEN Output LCD Panel Power Enable LCDDCLK Output LCD Panel Clock...
Page 93 LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC Table 5-2. LH75410 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES CTCLK Input Common External Clock TIMER 1 CTCAP1[A:B] Input Timer 1 Capture Inputs CTCMP1[A:B] Output Timer 1 Compare Outputs CTCLK Input Common External Clock TIMER 2 CTCAP2[A:B]...
Page 94 LH75410 SoC LH75400/01/10/11 (Preliminary) User’s Guide Table 5-2. LH75410 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES Input/Output General Purpose I/O Signals - Port E Input/Output General Purpose I/O Signals - Port F Input/Output General Purpose I/O Signals - Port G Input/Output General Purpose I/O Signals - Port H Input/Output General Purpose I/O Signals - Port I RESET, CLOCK, AND POWER CONTROLLER (RCPC)
Page 95 LH75400/01/10/11 (Preliminary) User’s Guide LH75410 SoC Table 5-2. LH75410 Signal Descriptions (Cont’d) PIN NO. SIGNAL NAME TYPE DESCRIPTION NOTES TEST INTERFACE TEST2 Input Test Mode Pin 2 TEST1 Input Test Mode Pin 1 Input JTAG Test Mode Select Input RTCK Output Returned JTAG Test Clock Output Input...
Page 96: Chapter 6 - Memory Interface Architecture
Chapter 6 Memory Interface Architecture The SHARP BlueStreak LH75400/01/10/11 devices provide the following data-path management resources on chip: • AHB and APB data buses • 16KB of zero-wait-state Tightly Coupled Memory (TCM) SRAM accessible via processor only • 16KB of internal SRAM accessible via processor, DMA, and LCD Controller •...
Page 97: Table 6-1. Memory Mapping
Memory Interface Architecture LH75400/01/10/11 (Preliminary) User’s Guide This memory map partition has three views, based on the setting of the REMAP bits in the Reset, Clock, and Power Controller. See Chapter 9. Table 6-1. Memory Mapping ADDRESS REMAP = 00 (DEFAULT) REMAP = 01 REMAP = 10 0x00000000...
Page 98: Table 6-2. External Memory Section Mapping
LH75400/01/10/11 (Preliminary) User’s Guide Memory Interface Architecture The second partitioning of memory space is the dividing of the segments into sections. The external memory segment is divided into eight 64MB sections, of which the first four are used, each having a chip select associated with it. Access to any of the last four sections does not result in an external bus access and does not cause a memory abort.
Page 99: Table 6-4. Apb Peripheral Register Mapping
Memory Interface Architecture LH75400/01/10/11 (Preliminary) User’s Guide Table 6-4. APB Peripheral Register Mapping ADDRESS RANGE DEVICE 0xFFFC0000 - 0xFFFC0FFF UART0 (16550) 0xFFFC1000 - 0xFFFC1FFF UART1 (16550) 0xFFFC2000 - 0xFFFC2FFF UART2 (82510) 0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter 0xFFFC4000 - 0xFFFC4FFF Timer Module CAN (LH75401 and LH75400) 0xFFFC5000 - 0xFFFC5FFF Reserved (LH75411 and LH75410)
Page 100: Chapter 7 - Static Memory Controller
Chapter 7 Static Memory Controller The Static Memory Controller (SMC) is an AMBA AHB slave peripheral. The SMC inter- faces the SoC to external memory devices. The SMC supports four banks of external memory. Each bank has a maximum size of 16MB. The ARM system supports 32 bits of address space.
Page 101: Smc Theory Of Operation
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide 7.2 SMC Theory of Operation After power-up, the SoC provides a single-chip select (nCS0) and 16 address bits (A[15:0]). The SoC can be reprogrammed to exchange GPIO for up to three more chip selects (nCS3 to nCS1) and up to eight more address bits (A[23:16]).
Page 102: Figure 7-1. Smc Write Access
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller Figure 7-1. SMC Write Access 6/17/03...
Page 103: Smc Read Process
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide There are a number of variations to the write process: • The nCSx signal will be de-asserted one cycle earlier if the next cycle is to be a write (see Figure 7-2). • If the external bus is not as wide as the data in the transaction, the SMC buffers the data and issues further external write cycles, modifying the address as needed to complete the transaction.
Page 104: Figure 7-2. Smc Write, Ncsx De-Asserted Early
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller Figure 7-2. SMC Write, nCSx De-asserted Early 6/17/03...
Page 105: Figure 7-3. Smc Read Access
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 7-3. SMC Read Access 6/17/03...
Page 106: Figure 7-4. Smc Burst Read Access
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller Figure 7-4. SMC Burst Read Access 6/17/03...
Page 107: External Memory Bus Cycle
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide 7.2.4 External Memory Bus Cycle As previously mentioned, the external memory bus cycle commences with the assertion of nCS(x) and ends when it is de-asserted. In addition to a programmable number of wait states for a read or write, the SoC supports a programmable number of wait states (from 1 to 32) for enabling the external bus to ‘turn around’...
Page 108: External Bus Read/Write Operations
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.2.5 External Bus Read/Write Operations Table 7-3 and Table 7-4 show how the SMC places data from the external bus onto the AHB based on the specified AHB control signals. Table 7-5 and Table 7-6 show how the SMC places data onto the external data bus and exercises the nBLE[1:0] signals based on the AHB control signals.
Page 109: Table 7-5. 8-Bit External Bus Write
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 7-5. 8-bit External Bus Write SYSTEM DATA MAPPING ACCESS: WRITE, 8-BIT EXTERNAL BUS ONTO EXTERNAL DATA BUS INTERNAL TRANSFER HSIZE[1:0] HADDR[1:0] A[1:0] nBLE[1:0] 15:8 WIDTH — 31:24 Word — 23:16 (4 transfers) —...
Page 110: Smc Memory Connection Diagram
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.2.6 SMC Memory Connection Diagram Figure 7-5 shows connections for a typical memory system with different data width memory devices. A[21:1] D[15:0] A[23:1] A[20:0] Q[31:0] D[15:0] nCS0 2M × 16 BURST MASK ROM A[16:1] D[15:0] A[15:0] IO[15:0]...
Page 111: Smc Programmer's Model
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide 7.3 SMC Programmer’s Model The base address for the SMC external memory (SMC MemBase) is: SMC MemBase Address: 0x40000000 (also 0x00000000 if REMAP is ‘00’) SMC memory banks have fixed address offsets from the base address. Table 7-7.
Page 112: Smc Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.3.2 SMC Register Definitions 7.3.2.1 Configuration Register for Memory Bank 0 Register BCR0 has a reset value of either 0x1000FFEF (for 16-bit Mode) or 0x0000FBEF (for 8-bit Mode). Table 7-9. BCR0 Register (16-bit Mode) FIELD RESET FIELD...
Page 113: Table 7-11. Bcr0 Register Definitions
Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 7-11. BCR0 Register Definitions BITS NAME DESCRIPTION Reserved Do not write. Must be set to 00. Unpredictable behavior if set to 31:30 any other value. Read as zero. Memory Width 00 = 8-bit 29:28 01 = 16-bit 10 = Reserved...
Page 114: Configuration Register For Memory Bank 1
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.3.2.2 Configuration Register for Memory Bank 1 BCR1 is the Configuration Register for Memory Bank 1. Table 7-12. BCR1 Register FIELD RESET FIELD WST2 WST1 IDCY RESET ADDR 0xFFFF1000 + 0x04 Table 7-13. BCR1 Register Definitions BITS NAME DESCRIPTION...
Page 115 Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 7-13. BCR1 Register Definitions (Cont’d) BITS NAME DESCRIPTION Wait State2 For SRAM: WST2 is the write access time burst access time for burst ROM. The wait state time is (WST2 + 1) × tHCLK. 15:11 WST2 For Burst ROM: WST2 is the burst access time.
Page 116: Configuration Register For Memory Bank 2
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.3.2.3 Configuration Register for Memory Bank 2 BCR2 is the Configuration Register for Memory Bank 2. Table 7-14. BCR2 Register FIELD RESET FIELD WST2 WST1 IDCY RESET ADDR 0xFFFF1000 + 0x08 Table 7-15. BCR2 Register Definitions BITS NAME DESCRIPTION...
Page 117 Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 7-15. BCR2 Register Definitions (Cont’d) BITS NAME DESCRIPTION Wait State2 For SRAM: WST2 is the write access time burst access time for burst ROM. The wait state time is (WST2 + 1) × tHCLK. 15:11 WST2 For Burst ROM: WST2 is the burst access time.
Page 118: Configuration Register For Memory Bank 3
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.3.2.4 Configuration Register for Memory Bank 3 BCR3 is the Configuration Register for Memory Bank 3. Table 7-16. BCR3 Register FIELD RESET FIELD WST2 WST1 IDCY RESET ADDR 0xFFFF1000 + 0x0C Table 7-17. BCR3 Register Definitions BITS NAME DESCRIPTION...
Page 119 Static Memory Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 7-17. BCR3 Register Definitions (Cont’d) BITS NAME DESCRIPTION Wait State2 For SRAM: WST2 is the write access time burst access time for burst ROM. The wait state time is (WST2 + 1) × tHCLK. 15:11 WST2 For Burst ROM: WST2 is the burst access time.
Page 120: Smc Default Memory Widths
LH75400/01/10/11 (Preliminary) User’s Guide Static Memory Controller 7.3.3 SMC Default Memory Widths At System Reset, the memory bank default external memory width is as shown in Table 7-18. Table 7-18. SMC System Reset Default Memory Width SMC MEMORY DEFAULT MEMORY WIDTH BANK Bank 0 Determined by the state of PD2/INT2 at Reset.
Page 121: Chapter 8 - Static Random Access Memory Controller
Static Random Access Memory Controller The SHARP BlueStreak LH75400/01/10/11 SoCs have 32KB of Static Random Access Memory (SRAM). This SRAM is organized into two 16KB blocks: • 16KB of Tightly Coupled Memory (TCM) 0 Wait State SRAM is available to the proces- sor as an ARM7TDMI-S bus slave.
Page 122: Chapter 9 - Reset, Clock, And Power Controller
Chapter 9 Reset, Clock, and Power Controller The Reset, Clock, and Power Controller (RCPC) lets users control System Reset, clocks, power management, and external interrupt conditioning via the AMBA APB interface. Figure 9-1 shows a block diagram of the RCPC. 14.7456 MHz OSCILLATOR 32.768 kHz OSCILLATOR PLL CLOCK...
Page 123: Rcpc Features
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.1 RCPC Features The RCPC provides the following features: • Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep, Stop1, and Stop2 • Generates the system clock (HCLK) from either the PLL clock or the PLL-bypassed (oscillator) clock, divided by 2, 4, 6, 8, …...
Page 124: Reset Generation
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller The RCPC manages five Power Modes: • Active • Standby • Sleep • Stop1 • Stop2. These modes let users reduce power consumption as necessary, with each mode provid- ing greater power savings (see Section 9.2.3 for more information). Active Mode is the nor- mal operating mode.
Page 125: Clock Generation
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.2.2 Clock Generation The RCPC generates the system clock, CPU clock, and on-chip peripheral clocks from the: • 14.7456 MHz crystal (connected to the XTALIN input pin and XTALOUT output pin) •...
Page 126: Active Mode
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.2.3.1 Active Mode Active Mode is the normal Power Mode. The SoC enters this mode after start-up and upon exiting any other Power Mode. After an External Reset, Watchdog Timer Reset, or Soft Reset is released, the System Reset is held active for an extra eight system clock cycles after the PLL is locked.
Page 127: Rcpc Programmer's Model
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3 RCPC Programmer’s Model The base address for the RCPC is: RCPC Base Address: 0xFFFE2000 The following locations are reserved and must not be used during normal operation: • Locations at offsets 0x01C through 0x20 •...
Page 128: Rcpc Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2 RCPC Register Definitions Except where noted, all registers are both writable and readable. Writing other than the default values to any reserved location and bit can cause the system to malfunction. 9.3.2.1 Control Register Ctrl is the Control Register.
Page 129: Identification Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.2 Identification Register ID is the Identification Register. This Read Only contains the last four digits of the part number encoded one part number digit per hex digit. The part number is encoded one part number digit per hex digit.
Page 130: Soft Reset Register
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2.4 Soft Reset Register SoftReset is the Soft Reset Register. This register provides a way for software to activate and deactivate the System Reset. SoftReset must reset the entire chip. The active bits used in this register are Read/Write.
Page 131: Reset Status Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.5 Reset Status Register ResetStatus is the Reset Status Register. This Read Only register provides the reset sta- tus of the device. It contains the external reset status and the WDT timeout reset status. At external reset, the EXT bit is set and the WDTO bit is cleared.
Page 132: Reset Status Clear Register
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2.6 Reset Status Clear Register ResetStatusClr is the Reset Status Clear Register. This Write Only register clears the Reset Status flags. When writing to this register, each HIGH data bit causes the corre- sponding bit in the Reset Status Register to be cleared.
Page 133: Hclk Prescaler Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.7 HCLK Prescaler Register SysClkPrescaler is the HCLK Prescaler Register. This register is a 4-bit value that holds the prescale count for the HCLK prescaler. The active bits used in this register are Read/Write.
Page 134: Peripheral Clock Control Register 0
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2.8 Peripheral Clock Control Register 0 APBPeriphClkCtrl0 is the Peripheral Clock Control Register 0. The active bits used in this register are Read/Write. This register controls the real-time, U2, U1, and U0 peripheral clocks. When writing to this register, setting a data bit to one stops the clock of the corresponding peripheral.
Page 135: Peripheral Clock Control Register 1
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.9 Peripheral Clock Control Register 1 APBPeriphClkCtrl1 is the Peripheral Clock Control Register 1. This register controls the LCD and SSP peripheral clocks. When writing to this register, setting a data bit to one stops the clock of the corresponding peripheral.
Page 136: Ahb Clock Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2.10 AHB Clock Control Register AhbClkCtrl is the AHB Clock Control Register. When writing to this register, setting a data bit to one stops the AHB DMA clock. Bit [1] of this register should never be cleared. The bit used in this register is Read/Write.
Page 137: Lcd Clock Prescaler Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.11 LCD Clock Prescaler Register LCDPrescaler is the LCD Clock Prescaler Register. The active bits used in this register are Read/Write. This register divides down the LCD clock frequencies using the appropriate formula: •...
Page 138: Ssp Clock Prescaler Register
LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller 9.3.2.12 SSP Clock Prescaler Register SSPPrescaler is the SSP Clock Prescaler Register. The active bits used in this register are Read/Write. This register divides down the SSP clock frequencies using the appropriate formula: •...
Page 139: External Interrupt Configuration Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.13 External Interrupt Configuration Register IntConfig is the External Interrupt Configuration Register. The active bits used in this reg- ister are Read/Write. This register configures the individual external interrupts to be either edge-sensitive or level-sensitive and either active HIGH or active LOW.
Page 140 LH75400/01/10/11 (Preliminary) User’s Guide Reset, Clock, and Power Controller Table 9-31. IntConfig Register Definitions (Cont’d) BITS FIELD NAME DESCRIPTION Configures External Interrupt INT2 00 = Configures INT2 to be a LOW-level trigger. INT2 01 = Configures INT2 to be a HIGH-level trigger. 10 = Configures INT2 to be a falling-edge trigger.
Page 141: External Interrupt Clear Register
Reset, Clock, and Power Controller LH75400/01/10/11 (Preliminary) User’s Guide 9.3.2.14 External Interrupt Clear Register IntClear is the External Interrupt Clear Register. The active bits used in this register are Write Only. This register individually clears active external interrupts. This register can only clear edge- triggered interrupts.
Page 142: Chapter 10 - Vectored Interrupt Controller
Chapter 10 Vectored Interrupt Controller The Vectored Interrupt Controller (VIC) provides the principle user interface to the interrupt system. 10.1 Theory of Operation All internal and external interrupts are routed to the VIC, where interrupt priority is deter- mined by hardware. The VIC is also where the appropriate signal to the processor (IRQ or FIQ) is generated.
Page 143: Vic Interrupt Listing
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide Any of the 32 lines can be assigned to any of the 16 interrupt vectors. Any line not explicitly assigned to an interrupt vector is processed as a default-vectored interrupt. At reset, all 32 lines are set to be default-vectored interrupts.
Page 144: Vectored Interrupts
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller Table 10-1. Interrupt Assignments POSITION DESCRIPTION SOURCE UART1 UARTTXINTR UART1 UART1 UARTINTR UART1 UART0 UARTINTR UART0 UART2 Interrupt UART2 CAN (LH75401 and LH75400) Reserved (LH75411 and LH75410) 10.1.3 Vectored Interrupts Each interrupt source line must be identified as either an IRQ type or an FIQ type using the IntSelect Register (see Section 10.2.2.4).
Page 145: Clearing Interrupts
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.1.5 Clearing Interrupts While the procedure for clearing an interrupt varies from source to source, general clearing actions must be performed: The interrupt must be cleared at its source, regardless of whether the interrupt source is external, internal, or software generated.
Page 146: Sequencing
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.1.7 Sequencing The sequence of interrupt processing in the SoCs are: An interrupt is asserted. One of the appropriate actions occurs: – If the interrupt is an external interrupt, the interrupt is conditioned by the RCPC to an active HIGH signal into the VIC.
Page 147 Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 11. After an FIQ or IRQ line into the CPU is asserted, the CPU takes over processing of the interrupt by switching internally to the applicable Processor Mode (either FIQ or IRQ). 12. If the interrupt is an FIQ interrupt, CPU processing should follow normal ARM conven- tions for processing FIQ interrupts.
Page 148: External Level-Sensitive Interrupts
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.1.8 External Level-Sensitive Interrupts When external interrupts are configured as level-sensitive, the ISR must ensure that there is a sufficient time between the time when the source of the external interrupt is cleared and the time when the interrupt at the VIC is cleared.
Page 149: Vic Register Summary
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.1 VIC Register Summary Table 10-2. VIC Register Summary RESET NAME ADDRESS OFFSET TYPE DESCRIPTION VALUE IRQStatus 0x00000000 IRQ Status Register 0x000 FIQStatus 0x004 0x00000000 FIQ Status Register RawIntr 0x008 — Raw Interrupt Status Register IntSelect 0x00C 0x00000000 Interrupt Select Register...
Page 150: Vic Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller Table 10-2. VIC Register Summary (Cont’d) RESET NAME ADDRESS OFFSET TYPE DESCRIPTION VALUE VectCtrl 12 0x230 0x00 Vector Control 12 Register VectCtrl 13 0x234 0x00 Vector Control 13 Register VectCtrl 14 0x238 0x00 Vector Control 14 Register VectCtrl 15 0x23C...
Page 151: Fiq Status Register
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.2 FIQ Status Register FIQStatus is the FIQ Status Register. This Read Only register provides the status of the interrupts after FIQ masking. Table 10-5. FIQStatus Register FIELD FIQStatus RESET FIELD FIQStatus RESET 0x004 ADDR 0xFFFFF000 +...
Page 152: Raw Interrupt Status Register
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.2.2.3 Raw Interrupt Status Register RawIntr is the Raw Interrupt Status Register. This Read Only register provides the status of the source interrupts (and software interrupts) to the Interrupt Controller. Table 10-7. RawIntr Register FIELD RawInterrupt RESET...
Page 153: Interrupt Select Register
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.4 Interrupt Select Register IntSelect is the Interrupt Select Register. This register selects whether the corresponding interrupt source generates an FIQ or an IRQ interrupt. Table 10-9. IntSelect Register FIELD IntSelect RESET FIELD IntSelect RESET 0x00C...
Page 154: Interrupt Enable Register
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.2.2.5 Interrupt Enable Register IntEnable is the Interrupt Enable Register. This register enables the interrupt request lines, by masking the interrupt sources for the IRQ interrupt. Table 10-11. IntEnable Register FIELD IntEnable RESET FIELD IntEnable RESET...
Page 155: Interrupt Enable Clear Register
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.6 Interrupt Enable Clear Register IntEnClear is the Interrupt Enable Clear Register. This register clears bits in the IntEnable Register (see Section 10.2.2.5). Table 10-13. IntEnClear Register FIELD IntEnable Clear RESET FIELD IntEnable Clear RESET 0x014 ADDR...
Page 156: Software Interrupt Register
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.2.2.7 Software Interrupt Register SoftInt is the Software Interrupt Register. This register generates software interrupts. Table 10-15. SoftInt Register FIELD SoftInt RESET FIELD SoftInt RESET 0x018 ADDR 0xFFFFF000 + Table 10-16. SoftInt Register Definitions NAME DESCRIPTION Generate Software Interrupt Setting a bit generates a software interrupt for...
Page 157: Software Interrupt Clear Register
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.8 Software Interrupt Clear Register SoftIntClear is the Software Interrupt Clear Register. This Write Only register clears bits in the SoftInt Register (see Section 10.2.2.7). Table 10-17. SoftIntClear Register FIELD SoftInt Clear RESET FIELD SoftInt Clear RESET...
Page 158: Vector Address Register
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.2.2.9 Vector Address Register VectAddr is the Vector Address Register. This register contains the ISR address of the cur- rently active interrupt. Reading from this register provides the address of the ISR, and indi- cates to the priority hardware that the interrupt is being serviced.
Page 159: Default Vector Address Register
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.10 Default Vector Address Register DefVectAddr is the Default Vector Address Register. This register contains the default ISR address. This address is used for non-vectored IRQs. Table 10-21. DefVectAddr Register FIELD Default VectorAddr RESET FIELD Default VectorAddr...
Page 160: Vector Address Registers
LH75400/01/10/11 (Preliminary) User’s Guide Vectored Interrupt Controller 10.2.2.11 Vector Address Registers There are 16 Vector Address Registers, designated VectAddr0 through VectAddr15. These registers contain the ISR vector addresses for the vectored IRQ interrupts. Table 10-23. VectAddr Registers FIELD VICVectorAddr RESET FIELD VICVectorAddr RESET...
Page 161: Vector Control Registers
Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide 10.2.2.12 Vector Control Registers There are 16 Vector Control Registers, designated VectCtrl0 through VectCtrl15. These registers select the interrupt source for the given vectored interrupt. The active bits used in these registers are Read/Wrote. Vectored interrupts are only generated if the interrupt is enabled.
Page 162: Chapter 11 - I/O Configuration
Chapter 11 I/O Configuration The I/O Configuration (IOCON) peripheral is an AMBA slave block that connects to the APB. The IOCON provides registers for programming the pin muxing on the device, and for controlling the pull-up and pull-down resistors on certain pins of the chip. 11.1 IOCON Theory of Operation All IOCON Control Registers can be accessed through the APB.
Page 163: Iocon Programmer's Model
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2 IOCON Programmer’s Model The base address for the IOCON is: IOCON Base Address: 0xFFFE5000 11.2.1 IOCON Register Summary Table 11-1. IOCON Register Summary ADDRESS RESET NAME TYPE DESCRIPTION OFFSET VALUE EBI_MUX 0x00 See Note EBI Interface Muxing Register PD_MUX 0x04 0x0000...
Page 164: Iocon Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration 11.2.2 IOCON Register Definitions Multi-bit pin configuration fields may have a bit setting called ‘Reset Condition’. Setting the bit field to this configures the pin to be the same as it would be set after a System Reset. 11.2.2.1 EBI Interface Muxing Register EBI_MUX is the EBI Interface Muxing Register.
Page 165: Table 11-4. Ebi_Mux Register Definitions
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide Table 11-4. EBI_MUX Register Definitions BITS NAME DESCRIPTION 31:15 Reserved Writing to these bits has no effect. Reading returns 0. PA7/D15 to PA0/D8 Source DATA 0 = PA7 to PA0 1 = D15 to D8 PB5/nWAIT Source nWAIT 0 = PB5...
Page 166: Pins Pd6/Int6 To Pd0/Int0 Muxing Register
LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration 11.2.2.2 Pins PD6/INT6 to PD0/INT0 Muxing Register PD_MUX is the Pins PD6/INT6 to PD0/INT0 Muxing Register. This register allows the sec- ondary function of the interrupt interface pins to be configured as GPIO. The active bits used in this register are Read/Write.
Page 167: Pins Pe7/Ssprm To Pd0/Int0 Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.3 Pins PE7/SSPRM to PD0/INT0 Muxing Register PE_MUX is the Pins PE7/SSPRM to PD0/INT0 Muxing Register. This register allows the secondary function of the pins to be configured as GPIO. The active bits used in this reg- ister are Read/Write.
Page 168: Table 11-9. Pe_Mux Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration Table 11-9. PE_MUX Register Definitions BITS NAME DESCRIPTION 31:10 Reserved Writing to these bits has no effect. Reading returns 0. PE7/SSPFRM Source SSPFRM 0 = PE7 1 = SSPFRM PE6/SSPCLK Source SSPCLK 0 = PE6 1 = SSPCLK PE5/SSPRX Source SSPRX...
Page 169: Timer Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.4 Timer Muxing Register TIMER_MUX is the Timer Muxing Register. This register allows the secondary function of the TIMER interface pins to be configured as GPIO. The active bits used in this register are Read/Write. Table 11-10.
Page 170 LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration Table 11-11. TIMER_MUX Register Definitions (Cont’d) BITS NAME DESCRIPTION PF1/CTCAP0D Source CTCAP0D 0 = PF1 1 = CTCAP0D PF0/CTCAP0C Source CTCAP0C 0 = PF0 1 = CTCAP0C Pin PG7/CTCAP1B/CTCMP0B Source 00 = PG7 CTCAP0B 01 = CTCAP0B 10 = CTCMP0B 11 = PG7...
Page 171: Lcd Mode Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.5 LCD Mode Muxing Register LCD_MUX is the LCD Mode Muxing Register. This register allows the LCD display to be configured to different modes supported by the SoC, freeing GPIO. The active bits used in this register are Read/Write.
Page 172: Pins Pa7/D15 To Pa0/D8 Resistor Muxing Register
LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration 11.2.2.6 Pins PA7/D15 to PA0/D8 Resistor Muxing Register PA_RES_MUX is the Pins PA7/D15 to PA0/D8 Resistor Muxing Register. This register allows the pull-up/pull-down to be configured as needed. The active bits used in this reg- ister are Read/Write.
Page 173 I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide Table 11-16. PA_RES_MUX Register Definitions (Cont’d) BITS NAME DESCRIPTION Pin PA2/D10 Resistor Source 00 = Pull-down 01 = Pull-up 10 = No pull-up or pull-down (default) 11 = Pull-up Pin PA1/D9 Resistor Source 00 = Pull-down 01 = Pull-up 10 = No pull-up or pull-down (default) 11 = Pull-up...
Page 174: Pins Pb5/Nwait To Pb0/Ncs1 Resistor Muxing Register
LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration 11.2.2.7 Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register PB_RES_MUX is the Pins PB5/nWAIT to PB0/nCS1 Resistor Muxing Register. This reg- ister allows the pull-up/pull-down to be configured as needed. The active bits used in this register are Read/Write.
Page 175: Pins Pc7/A23 To Pc0/A16 Resistor Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.8 Pins PC7/A23 to PC0/A16 Resistor Muxing Register PC_RES_MUX is the Pins PC7/A23 to PC0/A16 Resistor Muxing Register. This register allows the pull-up/pull-down to be configured as needed. The active bits used in this reg- ister are Read/Write.
Page 176 LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration Table 11-20. PC_RES_MUX Register Definitions (Cont’d) BITS NAME DESCRIPTION Pin PC2/A18 Resistor Source 00 = Pull-down (default) 01 = Pull-up 10 = No pull-up or pull-down 11 = Pull-down Pin PC1/A17 Resistor Source 00 = Pull-down (default) 01 = Pull-up 10 = No pull-up or pull-down 11 = Pull-down...
Page 177: Pins Pd6/Int6 To Pd0/Int0 Resistor Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.9 Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register PD_RES_MUX is the Pins PD6/INT6 to PD0/INT0 Resistor Muxing Register. This register allows the pull-up/pull-down to be configured as needed. The active bits used in this reg- ister are Read/Write.
Page 178 LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration Table 11-22. PD_RES_MUX Register Definitions (Cont’d) BITS NAME DESCRIPTION Pin PD1/INT1 Resistor Source 00 = Pull-down 01 = Pull-up 10 = No pull-up or pull-down (default) 11 = No pull-up or pull-down Pin PD0/INT0 Resistor Source 00 = Pull-down 01 = Pull-up 10 = No pull-up or pull-down (default)
Page 179: Pins Pe7/Ssprm To Pe0/Uartrx2 Resistor Muxing Register
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.10 Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register PE_RES_MUX is the Pins PE7/SSPRM to PE0/UARTRX2 Resistor Muxing Register. This register allows the pull-up/pull-down to be configured as needed. The active bits used in this register are Read/Write. The functions associated with bits [7:6] and [5:4] vary among the four SoCs: •...
Page 180 LH75400/01/10/11 (Preliminary) User’s Guide I/O Configuration Table 11-24. PE_RES_MUX Register Definitions (Cont’d) BITS NAME DESCRIPTION Pin PE4/SSPTX Resistor Source 00 = Pull-down (default) 01 = Pull-up 10 = No pull-up or pull-down 11 = Pull-down Pin PE3/CANTX/UARTTX0 Resistor Source (LH75400 and LH75401 SoC) Pin PE3/UARTTX0 Resistor Source (LH75410 and LH75411 SoC) 00 = Pull-down 01 = Pull-up (default)
Page 181: Pins An7/Pj7 To An0/Pj0
I/O Configuration LH75400/01/10/11 (Preliminary) User’s Guide 11.2.2.11 Pins AN7/PJ7 to AN0/PJ0 ADC_MUX is the Pins AN7/PJ7 to AN0/PJ0 Register. This register allows the secondary function of the ADC interface pins to be configured as General Purpose Inputs. The active bits used in this register are Read/Write. Table 11-25.
Page 182: Chapter 12 - Direct Memory Access Controller
Chapter 12 Direct Memory Access Controller The Direct Memory Access (DMA) Controller provides DMA support for the DMA-capable peripherals listed in Table 12-1. It is not used for the display system. The LCD Controller has its own DMA port for connecting directly to the memory system for retrieving display data.
Page 183: Dma Theory Of Operation
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide • Ability of each stream to indicate a transfer error via an interrupt • 16-word First-In, First Out (FIFO) array, with pack and unpack logic to handle all input/ output combinations of byte, half-word, and word transfers •...
Page 184 LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller The following steps summarize the DMA process: The external request signal (DREQ) starts a peripheral DMA transfer. The DMA Controller requests use of the AHB. When the AHB arbiter grants the AHB to the DMA Controller, the DMA Controller fills its FIFO with the number of data units specified by the burst length (1, 4, 8, or 16).
Page 185: Interrupt, Error, And Status Registers
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide 12.2.1 Interrupt, Error, and Status Registers The SoCs provide Interrupt, Error, and Status Registers for controlling the generation of an interrupt, error-handling control, and active-stream monitoring. Each stream has its own interrupt flag, which is set after the last transfer completes. Each of the four interrupt flags can be masked and cleared independently.
Page 186: Figure 12-1. Peripheral-To-Memory Data-Transfer Timing
LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller Figure 12-1. Peripheral-to-Memory Data-Transfer Timing 7/15/03 12-5...
Page 187: Figure 12-2. Memory-To-Peripheral Data-Transfer Timing
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 12-2. Memory-to-Peripheral Data-Transfer Timing 12-6 7/15/03...
Page 188: Dma Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller 12.3 DMA Programmer’s Model The base address for the DMA Controller is: DMA Base Address: 0xFFFE1000 The DMA Registers are accessed via the APB; the register data path is 16 bits wide. The register offsets for the DMA Controller are defined in Table 12-2.
Page 189: Dma Controller Register Definitions
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide 12.3.2 DMA Controller Register Definitions 12.3.2.1 Source Base Registers These two 16-bit registers contain the 32-bit source base address for the next DMA trans- fer. When the DMA Controller is enabled, the content of the Source Base Address Register is loaded in the Current Source Address Register.
Page 190: Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller 12.3.2.4 Control Register The Control Register reads and writes the configuration of the DMA Controller. The active bits used in this register are Read/Write. Table 12-4. CTRL Register FIELD RESET FIELD DeSize SoBurst SoSize RESET...
Page 191: Table 12-7. Dma Burst Size
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 12-5. CTRL Register Definitions (Cont’d) NAME FUNCTION Source-to-DMA data width See Table 12-6. For memory-to-peripheral operations, SoSize if bits [6:5] = ‘00’, bits [4:3] must = ‘00’. If bits [6:5] = ‘01’, bits [4:3] must = ‘01’. Current Destination Register Increment Enables the Current Destination Register increment after each DMA-to-destination data transfer.
Page 192: Current Source Registers
LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller 12.3.2.5 Current Source Registers The Current Source Registers are 16-bit Read Only registers that hold the current value of the source address pointer. The value in the registers is used as an AHB address in a source-to-DMA data transfer over the AHB.
Page 193: Interrupt Mask Register
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide 12.3.2.8 Interrupt Mask Register The Interrupt Mask Register selects the status flag that can generate an interrupt. When exiting Reset, the default value is 0x00. The active bits used in this register are Read/Write. Table 12-8.
Page 194: Interrupt Clear Register
LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller 12.3.2.9 Interrupt Clear Register The Interrupt Clear Register clears the status flags. The active bits used in this register are Write Only. This register has no default value after Reset. Table 12-10. CLR Register FIELD RESET FIELD...
Page 195: Status Register
Direct Memory Access Controller LH75400/01/10/11 (Preliminary) User’s Guide 12.3.2.10 Status Register The Status Register is a Read Only register that provides status information regarding the DMA Controller. The default value after Reset is 0x00. Table 12-12. Status Register FIELD RESET FIELD Int3 Int2...
Page 196 LH75400/01/10/11 (Preliminary) User’s Guide Direct Memory Access Controller The Int0-Int3 bits are the data stream interrupt flags corresponding to data stream0 through data stream3. A data stream sets its corresponding interrupt flag when a data transfer is completed (the whole packet has been transferred to its destination). The ErrorInt[3:0] bits are the Error interrupt flags corresponding to data stream0 through data stream3.
Page 197: Chapter 13 - Color Liquid Crystal Display Controller
Chapter 13 Color Liquid Crystal Display Controller The Color Liquid Crystal Display (LCD) Controller information in this section pertains to the LH75401 and LH75411 SoC devices only. The Color LCD Controller (CLCDC) is an AMBA master-slave module that connects to the AHB.
Page 198: Figure 13-1. Color Lcd Controller Block Diagram (Lh75401 And Lh75411 Only)
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 13-1. Color LCD Controller Block Diagram (LH75401 and LH75411 Only) 13-2 7/15/03...
Page 199: Clcdc Features
– Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/Grayscale. • Direct or Palletized colors • Single and dual panels • Supports Sharp and non-Sharp panels • CLCDC outputs available as General Purpose Inputs/Outputs (GPIOs) if LCDC is not needed •...
Page 200: Clcdc Theory Of Operation
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.2 CLCDC Theory of Operation The basic function of the CLCDC is to retrieve image data from system memory (the frame buffer), format the data for the LCD panel, and write it to the panel. The CLCDC also cre- ates the control signals that cause the panel to display the formatted data.
Page 201: How Pixels Are Stored In Memory
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.2.3 How Pixels are Stored in Memory Table 13-2 and Table 13-3 show the data structure in each DMA FIFO word corresponding to the bpp combinations. The required data for each panel display pixel must be extracted from the data word.
Page 202: Palette Ram
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.2.4 Palette RAM The CLCDC includes a 256 × 16 bit dual-port RAM-based palette. The least-significant bit of the serialized pixel data selects the upper or lower half of the palette RAM, based on the Byte Ordering Mode.
Page 203: Grayscale Algorithm
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.2.5 Grayscale Algorithm A patented grayscale algorithm drives the monochrome and color STN panels. • For monochrome displays, the gray-scale algorithm provides 15 gray scales. • For color displays, the 3-color components (red, green, and blue) are grayscaled simul- taneously.
Page 204: Table 13-5. Supported Tft, Hr-Tft, And Ad-Tft Lcd Panels
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide TFT, HR-TFT, and AD-TFT LCD panels utilize color palette RAM. For these panels, each 16-bit palette entry is composed of 5 bpp, plus a common intensity bit. In addition, the total number of supported colors can be doubled from 32,768 to 65,536 if the Intensity bit is uti- lized and applied simultaneously to all three color components (R, G, and B).
Page 205: Table 13-8. Color Stn Intensities From Gray-Scale Modulation
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller Table 13-8 shows the intensity that can be obtained from each of the 16 possible 4-bit pal- ette combinations. Only 15 of the combinations are useful because the two middle values produce the same result.
Page 206: Clcdc Programmer's Model
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3 CLCDC Programmer’s Model The base address for the CLCDC is: CLCDC Base Address: 0xFFFF4000 The following locations are reserved and must not be used during normal operation: • Locations at offsets 0x030 through 0x1FC •...
Page 207: Clcdc Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2 CLCDC Register Definitions 13.3.2.1 Horizontal Timing Panel Control Register The Timing0 Register controls: • Horizontal Synchronization Pulse Width (HSW) • Horizontal Front Porch (HFP) period • Horizontal Back Porch (HBP) period •...
Page 208: Horizontal Timing Restrictions
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.2 Horizontal Timing Restrictions The LCD DMA requests new data at the start of a horizontal display line. Some time must be allowed for the DMA transfer and for the data to propagate down the FIFO path in the LCD interface.
Page 209: Vertical Timing Panel Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2.3 Vertical Timing Panel Control Register The Timing1 Register controls the: • Number of Lines-Per-Panel (LPP) • Vertical Synchronization Pulse Width (VSW) • Vertical Front Porch (VFP) period • Vertical Back Porch (VBP) period Table 13-12.
Page 210: Clock And Signal Polarity Control Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.4 Clock and Signal Polarity Control Register The Timing2 Register controls the CLCDC timing. Table 13-14. Timing2 Register FIELD RESET FIELD RESET ADDR 0xFFFF4000 + 0x08 Table 13-15. Timing2 Register Definitions NAME DESCRIPTION 31:27...
Page 211: Upper Panel Frame Buffer Base Address Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2.5 Upper Panel Frame Buffer Base Address Register The UPBASE Register is one of two Color LCD DMA Base Address Registers (the other is LPBASE). Together with LPBASE, this Read/Write register programs the base address of the frame buffer.
Page 212: Lower Panel Frame Buffer Base Address Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.6 Lower Panel Frame Buffer Base Address Register The LPBASE Register is one of two Color LCD DMA Base Address Registers (the other is UPBASE). Together with UPBASE, this Read/Write register programs the base address of the frame buffer.
Page 213: Interrupt Enable Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2.7 Interrupt Enable Register INTRENABLE is the Interrupt Enable Register. Setting bits within this register enables the corresponding raw interrupt Status bit values to be passed to the Raw Interrupt Status Register (see Chapter 13).
Page 214: Lcd Panel Parameters, Lcd Panel Power, And Clcdc Control Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.8 LCD Panel Parameters, LCD Panel Power, and CLCDC Control Register Ctrl is a Read/Write register that controls the mode in which the CLCDC operates. The active bits used in this register are Read/Write. Table 13-22.
Page 215 LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller Table 13-23. Ctrl Register Definitions (Cont’d) NAME DESCRIPTION RGB or BGR Format Selection 0 = RGB normal output. 1 = BGR red and blue swapped. LCD Interface is Dual-Panel STN This bit has no meaning in other modes, program to zero.
Page 216: Raw Interrupt Status Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.9 Raw Interrupt Status Register Status is the Raw Interrupt Status Register. This register is Read/Write. • On a read, this register returns five bits that may generate interrupts when set. •...
Page 217: Final Masked Interrupts Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2.10 Final Masked Interrupts Register The Interrupt Register is a Read Only register. It is a bit-by-bit logical AND of the Raw Inter- rupt Status Register (see Section 13.3.2.9) and Interrupt Enable Register (see Section 13.3.2.7).
Page 218: Lcd Upper Panel Frame Buffer Current Address Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.2.11 LCD Upper Panel Frame Buffer Current Address Register UPCURR and LPCURR are registers that contain an approximate value of the upper and lower panel data DMA addresses when read. The registers can change at any time and provide a coarse indication of the current LCD DMA memory pointer.
Page 219: 16-Bit Color Palette Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.3.2.12 256 × 16-bit Color Palette Register The color map in the SoC of 65,535 colors is mapped into a group of palette entries, com- prising the Palette Registers. The upper four bits of each palette entry is used for best con- trast in STN displays.
Page 220: Clcdc Interrupts
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.3.3 CLCDC Interrupts The single combined interrupt, CLCDINTR, is used to drive the Vectored Interrupt Controller (VIC). If any of the four interrupt conditions occurs, this signal is asserted. CLCDINTR drives the VIC. Each of the four individual maskable interrupt conditions is enabled or disabled by chang- ing the mask bits in the INTRENABLE Register.
Page 221: Hrtftc Theory Of Operation
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.4.2 HRTFTC Theory of Operation All HRTFTC Control and Status Registers can be accessed through the APB. One of the registers, the Setup Register, can be programmed to select Bypass Mode or HR-TFT Mode.
Page 222: Hrtftc Register Definitions
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.4.5 HRTFTC Register Definitions 13.4.5.1 Setup Register The Setup Register enables Conversion mode or disables it so that signals from the LCDC pass through unaltered. It also configures the Pixels Per Line when in Conversion mode. The Pixels Per Line value in this register should be the same as the value entered in the Timing0 register.
Page 223: Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.4.5.2 Control Register CTRL is the Control Register. The Control Register enables and controls output signals. The active bits used in this register are Read/Write. Table 13-37. CTRL Register FIELD RESET FIELD RESET ADDR...
Page 224: Timing1 Register
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.4.5.3 Timing1 Register The Timing1 Register is used for various delays values for output signals. All delays are specified in number of LCD clock (LCDDCLK) periods. The active bits used in this register are Read/Write.
Page 225: Timing2 Register
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 13.4.5.4 Timing2 Register The Timing2 Register is used for various delay values for output signals. All delays are specified in number of LCD clock (LCDDCLK) periods. The active bits used in this register are Read/Write.
Page 226: Timing Waveforms
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 13.5 Timing Waveforms This section describes typical output waveform diagrams for the CLCDC and the HRTFTC. 13.5.1 STN Horizontal Timing Figure 13-2 shows typical horizontal timing waveforms for STN panels. In this figure, the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce the LCDDCLK output.
Page 227: Figure 13-2. Stn Horizontal Timing Diagram
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller Figure 13-2. STN Horizontal Timing Diagram 7/15/03 13-31...
Page 228: Figure 13-3. Stn Vertical Timing Diagram
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 13-3. STN Vertical Timing Diagram 13-32 7/15/03...
Page 229: Figure 13-4. Tft Horizontal Timing Diagram
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller Figure 13-4. TFT Horizontal Timing Diagram 7/15/03 13-33...
Page 230: Figure 13-5. Tft Vertical Timing Diagram
Color Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 13-5. TFT Vertical Timing Diagram 13-34 7/15/03...
Page 231: Figure 13-6. Hr-Tft Horizontal Timing Diagram
LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller 1 HR-TFT HORIZONTAL LINE CLCDCLK (INTERNAL) HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED APBPeriphClkCtrl1:LCD ClkPrescale:LCDPS (SHOWN FOR REFERENCE) Timing0:HSW LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2:BCD Timing2:IPC Timing2:CPL LCDVD[11:0] 002 003 004 005 006 007 008 PIXEL DATA Timing0:HSW + Timing0: HBP...
Page 232: Chapter 14 - Liquid Crystal Display Controller
Chapter 14 Liquid Crystal Display Controller The Liquid Crystal Display (LCD) Controller information in this section pertains to the LH75400 and LH75410 SoC devices only. The LCD Controller (LCDC) is an AMBA master-slave module that connects to the AHB. The LCDC translates pixel-coded data into the required formats and timings to drive single/dual monochrome LCD panels.
Page 233: Figure 14-1. Lcd Controller Block Diagram (Lh75400 And Lh75410 Only)
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide Figure 14-1. LCD Controller Block Diagram (LH75400 and LH75410 Only) 14-2 6/17/03...
Page 234: Lcdc Features
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.1 LCDC Features The LCDC supports: • Supported Monochrome STN Panels – Single-panel monochrome STN panels (4-bit and 8-bit bus interfaces) – Dual-panel monochrome STN panels (4-bit bus interface per panel) • Supported Resolutions –...
Page 235: Lcd Dma Fifos
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.2.1 LCD DMA FIFOs The upper and lower LCD DMA FIFOs can be independently controlled to cover single- and dual-panel LCD types. Each FIFO is 16 words deep by 32 bits wide. In single-panel STN Mode, the LCD DMA FIFOs are made to appear as a single FIFO of twice the size.
Page 236: Palette Ram
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.2.4 Palette RAM The LCDC includes a 256 × 16-bit dual-port RAM-based palette. The least-significant bit of the serialized pixel data is used to select between the upper and lower halves of the pal- ette RAM, based on the Byte Ordering Mode.
Page 237: Supported Grayscale
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide The LCDC has four individually maskable interrupt conditions going to a single combined interrupt. The single combined interrupt is asserted if any of the combined interrupt condi- tions are asserted and unmasked. Table 14-4.
Page 238: Lcdc Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3 LCDC Programmer’s Model The base address for the LCDC is: LDC Base Address: 0xFFFF4000 The following locations are reserved and must not be used during normal operation: • Locations at offsets 0x030 through 0x1FC •...
Page 239: Lcdc Register Definitions
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2 LCDC Register Definitions 14.3.2.1 Horizontal Timing Panel Control Register The Timing0 Register controls: • Horizontal Synchronization Pulse Width (HSW) • Horizontal Front Porch (HFP) period • Horizontal Back Porch (HBP) period •...
Page 240: Horizontal Timing Restrictions
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.2 Horizontal Timing Restrictions The LCD DMA requests new data at the start of a horizontal display line. Some time must be allowed for the DMA transfer and for the data to propagate down the FIFO path in the LCD interface.
Page 241: Vertical Timing Panel Control Register
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.3 Vertical Timing Panel Control Register The Timing1 Register controls the: • Number of Lines-Per-Panel (LPP) • Vertical Synchronization Pulse Width (VSW) • Vertical Front Porch (VFP) period • Vertical Back Porch (VBP) period Table 14-9.
Page 242: Clock And Signal Polarity Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.4 Clock and Signal Polarity Control Register The Timing2 Register controls the LCDC timing. Table 14-11. Timing2 Register FIELD RESET FIELD RESET ADDR 0xFFFF4000 + 0x08 Table 14-12. Timing2 Register Definitions NAME DESCRIPTION 31:27 Reserved Writing to these bits has no effect.
Page 243: Upper Panel Frame Buffer Base Address Register
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.5 Upper Panel Frame Buffer Base Address Register The UPBASE Register is one of two LCD DMA Base Address Registers (the other is LPBASE). Together with LPBASE, this Read/Write register programs the base address of the frame buffer.
Page 244: Lower Panel Frame Buffer Base Address Register
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.6 Lower Panel Frame Buffer Base Address Register The LPBASE Register is one of two LCD DMA Base Address Registers (the other is UPBASE). Together with UPBASE, this Read/Write register programs the base address of the frame buffer.
Page 245: Interrupt Enable Register
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.7 Interrupt Enable Register INTRENABLE is the Interrupt Enable Register. Setting bits within this register enables the corresponding raw interrupt Status bit values to be passed to the Interrupt Register. Table 14-17. INTRENABLE Register FIELD RESET FIELD...
Page 246: Lcd Panel Parameters, Lcd Panel Power, And Lcdc Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.8 LCD Panel Parameters, LCD Panel Power, and LCDC Control Register CTRL is a Read/Write register that controls the LCDC operating mode. Table 14-19. CTRL Register FIELD RESET FIELD LcdBpp RESET ADDR 0xFFFF4000 + 0x1C Table 14-20.
Page 247 Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide Table 14-20. CTRL Register Definitions (Cont’d) NAME DESCRIPTION Reserved Set to 0. LCD Interface is Dual-Panel STN This bit has no meaning in other modes, program to zero. LcdDual 0 = Single-panel LCD is in use. 1 = Dual-panel LCD is in use.
Page 248: Raw Interrupt Status Register
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.9 Raw Interrupt Status Register Status is the Raw Interrupt Status Register. This register is Read/Write. • On a read, this register returns five bits that may generate interrupts when set. • On writes to this register, a bit value of ‘1’ clears the interrupt corresponding to that bit. Writing a ‘0’...
Page 249: Final Masked Interrupts Register
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.10 Final Masked Interrupts Register The Interrupt Register is a Read Only register. It is a bit-by-bit logical AND of the Raw Inter- rupt Status Register (see Section 14.3.2.9) and INTRENABLE Register (see Section 14.3.2.7).
Page 250: Lcd Upper Panel Frame Buffer Current Address Register
LH75400/01/10/11 (Preliminary) User’s Guide Liquid Crystal Display Controller 14.3.2.11 LCD Upper Panel Frame Buffer Current Address Register UPCURR and LPCURR are registers that contain an approximate value of the upper and lower panel data DMA addresses when read. The registers can change at any time and provide a coarse indication of the current LCD DMA memory pointer.
Page 251: Lcd Palette Register
Liquid Crystal Display Controller LH75400/01/10/11 (Preliminary) User’s Guide 14.3.2.12 LCD Palette Register The color map in the SoC is 65,535 colors. These are mapped into a group of palette entries, comprising the Palette Registers. The upper four bits of each palette entry is used for best contrast.
Page 252: Chapter 15 - Timers
Chapter 15 Timers The timer block consists of three 16-bit timers: • Timer 0 has five Capture Registers and two Compare Registers. – Capture Registers: CAP0, CAP1, CAP2, CAP3, and CAP4 – Compare Registers: CMP0 and CMP1 • Timer 1 has two Capture Registers and two Compare Registers. –...
Page 253: Figure 15-1. Overall Timer Block Diagram
Timers LH75400/01/10/11 (Preliminary) User’s Guide CTCLK TIMER 0 BLOCK CAPTURE ADVANCED INPUT PERIPHERAL TIMER 0 COUNTER INPUT CAPTURE × 5 BUS (APB) COMPARE OUTPUT INTERRUPT INTERRUPT CONTROL COMPARE REGISTER × 2 REQUEST TIMER 1 BLOCK CAPTURE INPUT TIMER 1 COUNTER INPUT CAPTURE ×...
Page 254: Figure 15-2. Timer 0 Block Diagram
LH75400/01/10/11 (Preliminary) User’s Guide Timers INTERNAL EXTERNAL TO THE SoC TO THE SoC COMPARE COMPARE/CAPTURE REGISTERS CONTROL REGISTER CMP_CAP_CNTRL (TIMER0) CMP0 (TIMER0) CTCMP0A CMP1 (TIMER0) CTCMP0B ADVANCED PERIPHERAL CONTROL BUS (APB) REGISTER (ALL REGISTERS CNTRL (TIMER0) CONNECT TO INTERRUPT THIS BUS) CONTROL COUNTER REGISTER...
Page 255: Figure 15-3. Timers 1 And 2 Block Diagram
Timers LH75400/01/10/11 (Preliminary) User’s Guide INTERNAL EXTERNAL TO THE SoC TO THE SoC COMPARE CONTROL REGISTERS REGISTER ADVANCED CNTRL (TIMER0) CMP0 CTCMPxA PERIPHERAL BUS (APB) CMP1 CTCMPxB (ALL REGISTERS CONNECT TO THIS BUS) INTERRUPT COUNTER CONTROL REGISTER REGISTER COUNT CLOCK CTCLK INT_CNTRL COUNTER CLEAR...
Page 256: Timer Theory Of Operation
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.1 Timer Theory of Operation 15.1.1 Count Timing Each counter can use either one of the supported internal divided-by-n system clocks or an external clock as its count clock. Selection between one of the internal system clocks or the external clock is accomplished using the Timer Control Register that corresponds to the timer that is to be programmed.
Page 257: Counter Clear Upon Compare Match
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.1.2 Counter Clear Upon Compare Match A compare match occurs when the contents of the Timer Counter Register matches the value of the corresponding Timer Compare Register. When there is a compare match, one of two actions occurs, based on the setting of the TC bit in the corresponding Timer Control Register: •...
Page 258: Capture Signal Sampling
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.1.3 Capture Signal Sampling The capture signal is sampled on the rising edge of the system clock. The pulse width of a capture signal must be equal to or longer than two system clock periods plus, the setup time for the signal to be correctly read in.
Page 259: Figure 15-8. Pwm Output Signal Timing
Timers LH75400/01/10/11 (Preliminary) User’s Guide Figure 15-8 shows an example of PWM output signal timing. To support the timing shown in this figure, the following values need to be programmed into the registers. • CMP1 = 0x0005 → Period • CMP0 = 0x0001 → Period Timer 0 settings: •...
Page 260: Timer Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2 Timer Programmer’s Model The base address for the timers is: Timer Base Address: 0xFFFC4000 15.2.1 Timer Register Summary Table 15-1. Timer 0 Register Summary ADDRESS RESET NAME TYPE DESCRIPTION OFFSET VALUE CTRL 0x00 0x0000 Timer 0 Control Register CMP_CAP_CTRL 0x04...
Page 261: Timer Register Definitions
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2 Timer Register Definitions 15.2.2.1 Timer 0 Control Register Table 15-4. CTRL Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x00 Table 15-5. CTRL Register Definitions BITS FIELD NAME DESCRIPTION 31:5 Reserved Read as zero. Count Clock Select Specifies the system count clock.
Page 262: Timer 0 Compare/Capture Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.2 Timer 0 Compare/Capture Control Register CMP_CAP_CTRL is the Timer 0 Compare / Capture Control Register. Table 15-6. CMP_CAP_CTRL Register FIELD RESET FIELD CMP1 CMP0 CAP4 CAP3 CAP2 CAP1 CAP0 RESET ADDR 0xFFFC4000 + 0x04 Table 15-7.
Page 263 Timers LH75400/01/10/11 (Preliminary) User’s Guide Table 15-7. CMP_CAP_CTRL Register Definitions FIELD BITS DESCRIPTION NAME Input Edge Select Selects the rising edge, falling edge, both edges, or ignores all changes of the input signal that is used as the capture trigger. 00 = Capture input CTCAP0E is ignored CAP4 01 = Rising edge of CTCAP0E...
Page 264: Timer 0 Interrupt Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.3 Timer 0 Interrupt Control Register Table 15-8. INT_CTRL Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x08 Table 15-9. INT_CTRL Register Definitions BITS FIELD NAME DESCRIPTION 31:8 Reserved Read as zero. Timer 0 Interrupt Enable During Capture 4 Operation CAP4_EN 0 = No interrupt request occurs for capture 4.
Page 265: Timer 0 Status Register
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.4 Timer 0 Status Register The Status Register bits are independent of the individual interrupt enables. They are set to 1 upon all compare, capture, and overflow occurrences. To clear the status bits, write a 1 to the individual bits.
Page 266: Timer 0 Counter Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.5 Timer 0 Counter Register The CNT Register is a 16-bit, Read/Write up counter. The counter can be read or written to while it is operating. As a result, counts can be read at any time or the current count can be changed.
Page 267: Timer 0 Compare Registers
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.6 Timer 0 Compare Registers There are two CMP(n) Registers for Timer 0. They are designated: • CMP0 • CMP1 Each register is a 16-bit, read/write register. Contents of these registers are compared continuously with the counter CNT. When both register and counter values match, a trigger signal is generated.
Page 268: Timer 0 Capture Registers
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.7 Timer 0 Capture Registers There are five CAP(n) Registers for Timer 0. They are designated: • CAP0 • CAP1 • CAP2 • CAP3 • CAP4 Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT are stored into the associated Capture Register.
Page 269: Timer 1 Control Register
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.8 Timer 1 Control Register Table 15-18. CTRL Register FIELD RESET FIELD CMP1 CMP0 CAP1 CAP0 RESET ADDR 0xFFFC4000 + 0x30 Table 15-19. CTRL Register Definitions FIELD BITS DESCRIPTION NAME 31:15 Reserved Read as zero. PWM Output This bit allows the use of CTCMP1A as a PWM output.
Page 270 LH75400/01/10/11 (Preliminary) User’s Guide Timers Table 15-19. CTRL Register Definitions (Cont’d) FIELD BITS DESCRIPTION NAME Input Edge Select Selects the rising edge, falling edge, both edges, or ignores all changes of the input signal that is used as the capture trigger. 00 = Capture input CTCAP1B is ignored CAP1 01 = Rising edge of CTCAP1B...
Page 271: Timer 1 Interrupt Control Register
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.9 Timer 1 Interrupt Control Register Table 15-20. INT_CTRL Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x34 Table 15-21. INT_CTRL Register Definitions BITS FIELD NAME DESCRIPTION 31:5 Reserved Read as zero. Timer 1 Interrupt Enable During Capture 1 Operation CAP1_EN 0 = No interrupt request occurs for Capture 1.
Page 272: Timer 1 Status Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.10 Timer 1 Status Register The Status Register status bits are independent of the individual interrupt enables. They are set to 1 upon all compare, capture, and overflow occurrences. To clear the status bits, write 1s to the individual bits. This action clears the bit that was set in the register and clears the corresponding interrupt, with the following exception.
Page 273: Timer 1 Counter Register
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.11 Timer 1 Counter Register The CNT Register is a 16-bit, Read/Write up counter. The counter can be read or written to while it is operating. As a result, counts can be read at any time or the current count can be changed.
Page 274: Timer 1 Compare Registers
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.12 Timer 1 Compare Registers There are two CMP(n) Registers for Timer 1. They are designated: • CMP0 • CMP1 Each register is a 16-bit, Read/Write register. Contents of these registers are compared continuously with the counter CNT. When both register and counter values match, a trigger signal is generated.
Page 275: Timer 1 Capture Registers
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.13 Timer 1 Capture Registers There are two CAP(n) Registers for Timer 1. They are designated: • CAP0 • CAP1 Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT are stored into the associated Capture Register.
Page 276: Timer 2 Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.14 Timer 2 Control Register Table 15-30. CTRL Register FIELD RESET FIELD CMP1 CMP0 CAP1 CAP0 RESET ADDR 0xFFFC4000 + 0x50 Table 15-31. CTRL Register Definitions FIELD BITS DESCRIPTION NAME 31:15 Reserved Read as zero. PWM Output This bit allows the use of CTCMP2A as a PWM output.
Page 277 Timers LH75400/01/10/11 (Preliminary) User’s Guide Table 15-31. CTRL Register Definitions (Cont’d) FIELD BITS DESCRIPTION NAME Input Edge Select Selects the rising edge, falling edge, both edges, or ignores all changes of the input signal that is used as the capture trigger. 00 = Capture input CTCAP2B is ignored.
Page 278: Timer 2 Interrupt Control Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.15 Timer 2 Interrupt Control Register Table 15-32. INT_CTRL Register FIELD RESET FIELD RESET ADDR 0xFFFC4000 + 0x54 Table 15-33. INT_CTRL Register Definitions BITS FIELD NAME DESCRIPTION 31:5 Reserved Read as zero. Timer 2 Interrupt Enable During Capture Operation CAP1_EN 0 = No interrupt request occurs for Capture 1.
Page 279: Timer 2 Status Register
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.16 Timer 2 Status Register The Status Register bits are independent of the individual interrupt enables and are set to 1 upon all compare, capture, and overflow occurrences. To clear the status bits, write 1s to the individual bits.
Page 280: Timer 2 Counter Register
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.17 Timer 2 Counter Register The CNT Register is a 16-bit, read/write up counter. The counter can be read or written to while it is operating. As a result, counts can be read at any time or the current count can be changed.
Page 281: Timer 2 Compare Registers
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.18 Timer 2 Compare Registers There are two CMP(n) Registers for Timer 2. They are designated: • CMP0 • CMP1 Each register is a 16-bit, Read/Write register. Contents of these registers are compared continuously with the counter CNT. When both register and counter values match, a trigger signal is generated.
Page 282: Timer 2 Capture Registers
LH75400/01/10/11 (Preliminary) User’s Guide Timers 15.2.2.19 Timer 2 Capture Registers There are two CAP(n) Registers for Timer 2. They are designated: • CAP0 • CAP1 Each register is a 16-bit, Read Only register. When a capture condition occurs, the con- tents of the counter CNT are stored into the associated Capture Register.
Page 283: Timer Interrupts
Timers LH75400/01/10/11 (Preliminary) User’s Guide 15.2.2.20 Timer Interrupts The timer interrupts are: • Timer 0 Combined Interrupt — a combined interrupt formed by ORing the two compare, five capture, and one overflow interrupts in Timer 0. • Timer 1 Combined Interrupt — a combined interrupt formed by ORing the two compare, two capture, and one overflow interrupts in Timer 1.
Page 284: Chapter 16 - Watchdog Timer
Chapter 16 Watchdog Timer The Watchdog Timer (WDT) is a programmable timer that software has to reset at regular intervals. Failing to reset the timer causes an interrupt to the system. Failing to service the interrupt within the timeout period causes the WDT to set a flag that forces the RCPC to generate a System Reset.
Page 285: Wdt Theory Of Operation
Watchdog Timer LH75400/01/10/11 (Preliminary) User’s Guide 16.2 WDT Theory of Operation All Control and Status Registers for the Watchdog Timer can be accessed through the APB. The Watchdog Timer consists of a 32-bit down-counter that causes a selectable time-out interval to detect malfunctions. The timer needs to be periodically reset by soft- ware.
Page 286: Wdt Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Watchdog Timer 16.3.1 WDT Register Definitions 16.3.1.1 Control Register CTRL is the Control Register. The active bits used in this register are Read/Write. Table 16-2. CTRL Register FIELD RESET FIELD RESET ADDR 0xFFFE3000 + 0x00 Table 16-3. CTRL Register Definitions BITS NAME DESCRIPTION 31:8...
Page 287: Counter Reset Register
Watchdog Timer LH75400/01/10/11 (Preliminary) User’s Guide 16.3.1.2 Counter Reset Register CNTR is the Counter Reset Register. The active bits used in this register are Write Only. Table 16-4. CNTR Register FIELD RESET FIELD WDCNTR RESET ADDR 0xFFFE3000 + 0x04 Table 16-5. CNTR Register Definitions BITS NAME DESCRIPTION...
Page 288: Status Register
LH75400/01/10/11 (Preliminary) User’s Guide Watchdog Timer 16.3.1.3 Status Register STR is the Status Register. Table 16-6. STR Register FIELD RESET FIELD RESET ADDR 0xFFFE3000 + 0x08 Table 16-7. STR Register Definitions BITS NAME DESCRIPTION 31:8 Reserved Writing to these bits has no effect. Reading returns 0. nWDINTR Interrupt Status nWDINTR 1 = WDT interrupt has triggered.
Page 289: Counter Section 0 Register
Watchdog Timer LH75400/01/10/11 (Preliminary) User’s Guide 16.3.1.4 Counter Section 0 Register CNT0 is the Counter Section 0 Register. Table 16-8. CNT0 Register FIELD RESET FIELD Counter Sub-Section 0 RESET ADDR 0xFFFE3000 + 0x0C Table 16-9. CNT0 Register Definitions BITS NAME DESCRIPTION 31:8 Reserved Writing to these bits has no effect.
Page 290: Counter Section 2 Register
LH75400/01/10/11 (Preliminary) User’s Guide Watchdog Timer 16.3.1.6 Counter Section 2 Register CNT2 is the Counter Section 2 Register. Table 16-12. CNT2 Register FIELD RESET FIELD Counter Sub-Section 2 RESET ADDR 0xFFFE3000 + 0x14 Table 16-13. CNT2 Register Definitions BITS NAME DESCRIPTION 31:8 Reserved Writing to these bits has no effect.
Page 291: Chapter 17 - Real-Time Clock
Chapter 17 Real-Time Clock The Real Time Clock (RTC) is an AMBA slave module that connects to the APB. The RTC can provide a basic alarm function or act as a long-time base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of an RTC input.
Page 292: Rtc Theory Of Operation
Real-Time Clock LH75400/01/10/11 (Preliminary) User’s Guide 17.2 RTC Theory of Operation The SoC reads and writes data and control/status information via the AMBA APB interface. The 32-bit counter increments on successive rising edges of the 1 Hz clock from the RCPC.
Page 293: Rtc Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide Real-Time Clock 17.3 RTC Programmer’s Model The base address for the RTC is: RTC Base Address: 0xFFFE0000 17.3.1 RTC Register Summary Table 17-1. RTC Register Summary ADDRESS RESET NAME TYPE DESCRIPTION OFFSET VALUE 0x00 Lower 16-bit Data Register 0x04 Upper 16-bit Data Register 0x08...
Page 294: Rtc Register Definitions
Real-Time Clock LH75400/01/10/11 (Preliminary) User’s Guide 17.3.2 RTC Register Definitions 17.3.2.1 Data Register 0 DR0 is the Lower 16-bit Read Data Register. Reads from this register return the current value of the lower 16 bits of the counter. When this register is read, the DR1 Register is updated with the current value of the upper 16 bits of the counter.
Page 295: Data Register 1
LH75400/01/10/11 (Preliminary) User’s Guide Real-Time Clock 17.3.2.2 Data Register 1 DR1 is the Upper 16-bit Read Data Register. Reads from this register return the value of the upper 16 bits of the counter when DR0 was last accessed. The DR0 Register should be read before reading the DR1 Register to avoid the mismatch between the DR0 and the DR1 Registers due to a counter rollover.
Page 296: Match Register 0
Real-Time Clock LH75400/01/10/11 (Preliminary) User’s Guide 17.3.2.3 Match Register 0 MR0 is the Lower 16-bit Read/Write Match Register. Writes to this register load the lower 16-bit Match Register. Reads return the last written value. Table 17-6. MR0 Register FIELD RESET —...
Page 297: Interrupt Status/Clear
LH75400/01/10/11 (Preliminary) User’s Guide Real-Time Clock 17.3.2.5 Interrupt Status/Clear STAT/EOI is the Interrupt Status/Clear Register. The write location is a virtual address with no physical storage element. A write to this location clears the RTCINTR interrupt line and the corresponding status bit. A read from bit 0 returns the value of RTCINTR. Table 17-10.
Page 298: Read/Write Load Register 0
Real-Time Clock LH75400/01/10/11 (Preliminary) User’s Guide 17.3.2.6 Read/Write Load Register 0 LR0 is the Lower 16-bit Read/Write Load Register. Writes to this register load the least- significant 16 bits of an Intermediate Register. The intermediate Register is not loaded into the free-running counter until the rising edge of a 1 Hz clock follows a write operation to LR1.
Page 299: Read/Write Load Register 1
LH75400/01/10/11 (Preliminary) User’s Guide Real-Time Clock 17.3.2.7 Read/Write Load Register 1 LR1 is the Upper 16-bit Read/Write Load Register. Writes to this register load the most- significant 16 bits of an Intermediate Register. The Intermediate Register is not loaded into the free-running counter until the rising edge of CLK1HZ.
Page 300: Control Register
Real-Time Clock LH75400/01/10/11 (Preliminary) User’s Guide 17.3.2.8 Control Register CTRL is a 1-bit Control Register that controls the masking of the interrupt generated by the RTC. Writing a ‘1’ to bit position 0 enables the interrupt. Writing a ‘0’ disables the interrupt. Reads to this register return the last value written at bit position 0.
Page 301: Chapter 18 - Synchronous Serial Port
Chapter 18 Synchronous Serial Port The Synchronous Serial Port (SSP) is a master-only interface for synchronous serial communication with slave peripheral devices that have Motorola SPI, National Semicon- ductor Microwire, or Texas Instruments DSP-compatible synchronous serial interfaces. Figure 18-1 shows a block diagram of the SSP. 18.1 SSP Features The SSP block provides the following features.
Page 302: Figure 18-1. Synchronous Serial Port Block Diagram
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide Figure 18-1. Synchronous Serial Port Block Diagram 18-2 6/17/03...
Page 303: Ssp Theory Of Operation
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.2 SSP Theory Of Operation The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories. These memo- ries can store eight 16-bit values independently in both transmit and receive modes. Serial data is transmitted on SSPTX and received on SSPRX.
Page 304: Ssp Timing Waveforms
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.3 SSP Timing Waveforms Figure 18-2 shows the standard set of SSP timing waveforms. Figure 18-2. SSP Timing Waveform 18-4 6/17/03...
Page 305: Motorola Spi Frame Format
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.3.1 Motorola SPI Frame Format For the Motorola SPI format, the serial frame pin (SSPFRM) is active LOW. The SPO and SPH bits in SSP Control Register 0 influence SSPCLK and SSPFRM operation in Single and Continuous Modes.
Page 306 Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide SSPCLK (SPO = 0) SSPCLK (SPO = 1) SSPTX (from master) SSPRX LSB Q (from slave) SSPFRM NOTE: Q = Undefined. LH754xx-33 Figure 18-5. Motorola SPI Frame Format with SPH = 0 SCLK (SPO = 0) SCLK (SPO = 1)
Page 307: Texas Instruments Frame Format
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.3.2 Texas Instruments Frame Format For the Texas Instruments DSP-compatible synchronous serial interface frame format, the SSPFRM pin is pulsed for one serial clock period stating at its rising edge, prior to each frame's transmission.
Page 308: National Semiconductor Frame Format
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.3.3 National Semiconductor Frame Format Unlike the full-duplex transmission capabilities that the other two frame formats support, the National Semiconductor Microwire format uses a special half-duplex, master-slave messaging technique. In this mode: When a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmission, the SSP does not receive incoming data.
Page 309: Figure 18-9. Microwire Frame Format (Single Transfer)
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port Figure 18-9. Microwire Frame Format (Single Transfer) 6/17/03 18-9...
Page 310: Figure 18-10. Microwire Frame Format (Continuous Transfers)
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide Figure 18-10. Microwire Frame Format (Continuous Transfers) 18-10 6/17/03...
Page 311: Ssp Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.5 SSP Programmer’s Model The base address for the SSP is: SSP Base Address: 0xFFFC6000 Locations at offsets 0x01C through 0xFFF are reserved and must not be used during nor- mal operation. 18.5.1 SSP Register Summary Table 18-2.
Page 312: Ssp Register Definitions
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.5.2 SSP Register Definitions 18.5.2.1 Control Register 0 CTRL0 is Control Register 0. CTRL0 contains five bit fields that control various SSP functions. The active bits used in this register are Read/Write. Table 18-3. CTRL0 Register FIELD RESET FIELD...
Page 313: Control Register 1
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.5.2.2 Control Register 1 CTRL1 is the Control Register 1. CTRL1 contains five bit fields that control various SSP functions. The active bits used in this register are Read/Write. Table 18-5. CTRL1 Register FIELD RESET FIELD...
Page 314: Receive / Transmit Fifo Register
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.5.2.3 Receive / Transmit FIFO Register DR is the 16-bit-wide Receive / Transmit FIFO register. The active The active bits used in this register are Read/Write. • When DR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed.
Page 315: Status Register
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.5.2.4 Status Register SR is the Status Register. This register contains bits that indicate the FIFO fill status and the SSP busy status. Table 18-9. SR Register FIELD RESET FIELD RESET ADDR 0xFFFC6000 + 0x00C Table 18-10.
Page 316: Clock Prescale Register
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.5.2.5 Clock Prescale Register CPSR is the Clock Prescale Register. The CPSR Register specifies the division factor by which the input HCLK should be internally divided before further use. The active bits used in this register are Read/Write.
Page 317: Interrupt Identification/Clear Register
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.5.2.6 Interrupt Identification/Clear Register IIR is the Interrupt Identification Register. The interrupt status is read from this register. ICR is the Interrupt Clear Register. A write of any value to this register clears the SSP receive FIFO Overrun Interrupt.
Page 318: Receive Timeout Register
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide Table 18-15. IIR/ICR Register (Write Characteristic) FIELD RESET FIELD RESET ADDR 0xFFFC6000 + 0x014 Table 18-16. IIR/ICR Register Definitions (Write Characteristic) BITS NAME DESCRIPTION 31:16 Reserved Writing to these bits has no effect. Clear Receive Overrun Interrupt A write to these bits clears the Receive 15:0 Overrun Interrupt, regardless of the data value written.
Page 319: Receive Interrupt
LH75400/01/10/11 (Preliminary) User’s Guide Synchronous Serial Port 18.5.3 SSP Interrupts The SSP can assert four interrupts: • SSPRXINTR — SSP Receive FIFO Service Interrupt request, locally maskable • SSPTXINTR — SSP Transmit FIFO Service Interrupt request, locally maskable • SSPRORINTR — SSP Receive Overrun Interrupt request, locally maskable •...
Page 320: Receive Timeout Interrupt
Synchronous Serial Port LH75400/01/10/11 (Preliminary) User’s Guide 18.5.3.4 Receive Timeout Interrupt SSPRXTOINTR is the Receive Timeout Interrupt. This interrupt is asserted if the receive FIFO does not generate a further service request interrupt (SSPRXINTR) within the num- ber of HCLK periods programmed in the RXTO Register. 18.5.3.5 SSPINTR The SSPRXINTR, SSPTXINTR, SSPRORINTR, and SSPRXTOINTR interrupts are also combined into the single output SSPINTR.
Page 321: Chapter 19 - Uart0 And Uart1
Chapter 19 UART0 and UART1 UART0 and UART1 offer similar internal functionality to the industry-standard 16C550. They perform serial-to-parallel conversion on data received from a peripheral device and parallel-to-serial conversion on data transmitted to the UART. The CPU reads and writes data and control/status information through the AMBA APB interface.
Page 322: Uart0 And Uart1 Features
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.1 UART0 and UART1 Features UART0 and UART1 provide the following features: • Supports baud rates up to 921,600 baud (given an external crystal frequency of 14.756 MHz) • Support for 5, 6, 7, or 8 data bits per character •...
Page 323: Status Conditions
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 The UART receiver is in the marking state (i.e., the input is 1) from the time a stop bit is sent until the time the next start bit is received. When the receiver receives an entire frame, the UART transfers the received data and the frame status to the receiver FIFO.
Page 324: On-Chip Dma Capabilities
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.2.3 On-Chip DMA Capabilities UARTs 0 and 1 can be programmed to utilize the on-chip DMA to reduce processor band- width required to service UART activities. DMA functions support burst transfers on the receive channel, transmission channel, or both.
Page 325: Uart0 And Uart1 Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3 UART0 and UART1 Programmer’s Model While UART0 and UART1 offer similar internal functionality to the industry standard 16C550, the programmer’s interface differs. That information is covered here. The base address for UART0 is: UART0 Base Address: 0xFFFC0000 The base address for UART1 is: UART1 Base Address: 0xFFFC1000...
Page 326: Uart0 And Uart1 Register Definitions
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1 UART0 and UART1 Register Definitions 19.3.1.1 Data Register DR is the Data Register for words that are to be transmitted or have been received over the serial interface. Writing to this register initiates transmission from the UART. •...
Page 327: Table 19-3. Dr Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 Table 19-3. DR Register Definitions NAME DESCRIPTION 31:12 Reserved Do not modify. Read as zero. Receive FIFO Full/Empty OVERRUN 0 = There is an empty space in the FIFO and a new character can be written ERROR to it.
Page 328: Receive Status/Error Clear Register
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.2 Receive Status/Error Clear Register RSR/ECR is the Receive Status Register/ Error Clear Register. If the status is read from this register, the status bits in this register correspond to the status bits of the last word read from the DR Register. The status information for overrun is set immediately when an overrun condition occurs.
Page 329: Table 19-6. Rsr/Ecr Register (Read Operations)
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 Table 19-6 and Table 19-7 describe the RSR/ECR Register for read operations. Table 19-6. RSR/ECR Register (Read Operations) FIELD RESET FIELD RESET UART0: 0xFFFC0000 + 0x004 ADDR UART1: 0xFFFC1000 + 0x004 Table 19-7. RSR/ECR Register Definitions (Read Operations) BITS NAME DESCRIPTION...
Page 330: Flag Register
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.3 Flag Register FR is the Flag Register. After System Reset, TXFF, RXFF, and BUSY are ‘0’, and TXFE and RXFE are ‘1’. Table 19-8. FR Register FIELD RESET FIELD RESET UART0: 0xFFFC0000 + 0x018 ADDR UART1: 0xFFFC1000 + 0x018 Table 19-9.
Page 331: Uart Line Control Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.4 UART Line Control Register The LCTRL Register is a single 30-bit register formed from three registers in the address map: • LCTRL_H • IBRD • FBRD. The 30 bits of LCR are updated when LCR_H is written. Table 19-10 shows how to update the contents of the register.
Page 332: Integer Baud Rate Divisor Register
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.5 Integer Baud Rate Divisor Register IBRD is the integer part of the baud rate divisor value. The active bits used in this register are Read/Write. All of the bits in this register clear to ‘0’ on System Reset. Table 19-11.
Page 333: Fractional Baud Rate Divisor Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.6 Fractional Baud Rate Divisor Register FBRD is the fractional part of the baud rate divisor value. The active bits used in this reg- ister are Read/Write. All the bits are cleared to ‘0’ on System Reset. All the bits are cleared to ‘0’...
Page 334: Calculating The Divisor Value
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.7 Calculating the Divisor Value The following example shows how to clear a divisor value. This example assumes that the required baud rate is 230,400 and the UARTCLK = 4 MHz. Baud Rate Divisor = (4 × 10 ) ÷...
Page 335: Line Control Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.9 Line Control Register LCTRL_H is the Line Control Register. The active bits used in this register are Read/Write. This register accesses bits [29:22] of the UART LCTRL Register (see Section 19.3.1.4). The contents of the LCTRL_H Register are not updated until transmission or reception of the current character is complete.
Page 336: Table 19-17. Lctrl_H Register Definitions
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide Table 19-17. LCTRL_H Register Definitions NAME DESCRIPTION 31:8 Reserved Read as zero. STICK PARITY Stick Parity Select Bits [7], [2], and [1] work together to set up the SELECT parity. See Table 19-18. Word Length Indicates the number of data bits transmitted or received in a frame.
Page 337: Uart Control Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.10 UART Control Register CTRL is the UART Control Register. To enable transmission, bit [8] and bit [0] must be set. Similarly, to enable reception, bit [9] and bit [0] must be set. The active bits used in this register are Read/Write.
Page 338: Interrupt Fifo Level Select Register
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.11 Interrupt FIFO Level Select Register IFLS is the Interrupt FIFO Level Select Register. The active bits used in this register are Read/Write. The IFLS Register defines the FIFO level at which interrupts are generated to request ser- vice for the receive and transmit FIFOs.
Page 339: Interrupt Mask Set/Clear Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.12 Interrupt Mask Set/Clear Register IMSC is the Interrupt Mask Set/Clear Register. The active bits used in this register are Read/Write. On a read, this register returns the current value of the mask on the relevant interrupt. On a write of ‘1’...
Page 340 UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide Table 19-24. IMSC Register Definitions (Cont’d) BITS NAME DESCRIPTION Receive Timeout Interrupt Mask Write values: RECEIVE TIMEOUT 0 = Clears the mask. INTERRUPT MASK 1 = Sets the mask of the RTIM interrupt. When Read, returns the current mask for the RTIM interrupt.
Page 341: Raw Interrupt Status Register
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.13 Raw Interrupt Status Register RIS is the Raw Interrupt Status Register. On a read, this register returns the current raw status value of the corresponding interrupt. A write has no effect. Table 19-25. RIS Register FIELD RESET FIELD...
Page 342: Masked Interrupt Status Register
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.14 Masked Interrupt Status Register MIS is the Masked Interrupt Status Register. On a read, this register returns the current masked status value of the corresponding interrupt. A write has no effect. Table 19-27. MIS Register FIELD RESET FIELD...
Page 343: Icr
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.1.15 ICR ICR is the Interrupt Clear Register. The active bits used in this register are Write Only. On a write of ‘1’, the corresponding interrupt is cleared. A write of ‘0’ has no effect. Table 19-29.
Page 344: Dmactrl
UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide 19.3.1.16 DMACTRL DMACTRL is the DMA Control Register. The active bits used in this register are Read/ Write. All the bits are cleared to ‘0’ on System Reset. Table 19-31. DMACTRL Register Definitions NAME DESCRIPTION 15:3...
Page 345: Uart0 And Uart1 Interrupts
LH75400/01/10/11 (Preliminary) User’s Guide UART0 and UART1 19.3.2 UART0 and UART1 Interrupts Both UART0 and UART1 have a combined interrupt. Only UART1 has separate UARTRXINTR and UARTTXINTR. The individual UART interrupt outputs are OR’d together to produce the combined interrupt for UART0 and UART1. However, UART1 has separate UARTRXINTR and UARTTXINTR interrupts.
Page 346: Chapter 20 - Uart2
Chapter 20 UART2 The UART2 peripheral offers similar functionality to the industry standard 82510. It per- forms serial-to-parallel conversion on data received from a peripheral device and parallel- to-serial conversion on data transmitted to the peripheral device. The CPU reads and writes data and control/status information through the AMBA APB interface.
Page 347: Uart2 Features
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.1 UART2 Features UART2 provides the following features: • Supports baud rates up to 3,225,600 baud (given a system clock of 70 MHz) • Support for 5, 6, 7, 8, or 9 data bits per character •...
Page 348: Uart Receiver Data Frame
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.2.1 UART Receiver Data Frame A UART receiver data frame has the following structure: • A start bit that indicates the beginning of the frame. The start bit consists of a ‘0’ on the receiver input for one bit period. •...
Page 349 UART2 LH75400/01/10/11 (Preliminary) User’s Guide The start bit works with the system clock to synchronize the receiver with the source driving the receiver. The start-bit verification can be performed through a majority-voting system or an absolute voting system. • With absolute voting, all samples must agree. Otherwise, a false start bit is determined and the receiver returns to the Start Bit Search Mode.
Page 350: Status Conditions
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.2.2 Status Conditions UART2 adheres to the following status conditions: • If the UART fails to detect a 1 for all programmed stop-bit periods following a data frame, the UART sets the framing-error status for that frame. •...
Page 351: Baud Rate Generators
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.2.4 Baud Rate Generators UART2 has two 16-bit baud-rate generators. These baud-rate generators are completely independent of each other and can be separately configured as timers. Dividing the system clock with the divisor count generates the baud rate. Either baud-rate generator can clock either serial machine (transmitter or receiver).
Page 352: Uart2 Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3 UART2 Programmer’s Model The base address for UART2 is: UART2 Base Address: 0xFFFC2000 20.3.1 UART2 Register Summary The Configuration, Status, and Control Registers are contained in one of four banks. Selection of banks 0 to 3 is accomplished by writing to the GIR Register bits 6 and 5. The GIR Register is accessible at the same address for all register banks.
Page 353: Register Bank 0
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.1.2 Register Bank 1 Table 20-2. Register Bank 1 ADDRESS RESET NAME DLAB TYPE DESCRIPTION OFFSET VALUE 0x00 Transmit Buffered Data Register 0x00 0x00 Receive Buffered Data Register 0x04 Transmit Character Flag Register 0x04 0x40 Receive Character Flag Register General Interrupt Register/Bank Register 0x08...
Page 354 LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.1.4 Register Bank 3 Table 20-4. Register Bank 3 ADDRESS RESET NAME DLAB TYPE DESCRIPTION OFFSET VALUE CLCF 0x00 0x00 Clocks Configure Register BACF 0x04 0x04 BRGA Configuration Register BRGB Divisor LSB Register. The DLAB bit in the LCR 0x00 0x05 Register needs to be set to access this register.
Page 355: Uart2 Register Definitions
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2 UART2 Register Definitions 20.3.2.1 Transmit Buffered Data Register Register Banks: 0 and 1 TXD is the Transmit Buffered Data Register. The active bits used in this register are Write Only. The TXD Register holds the next data byte to be pushed into the Transmit FIFO. Table 20-5.
Page 356: Receive Buffered Data Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.2 Receive Buffered Data Register Register Banks: 0 and 1 RXD is the Receive Buffered Data Register. The RXD Register holds the earliest received character in the Rx FIFO After System Reset, this register is undefined. Table 20-7.
Page 357: Brga Divisor Least Significant Byte Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.3 BRGA Divisor Least Significant Byte Register Register Bank: 0 BAL is the BRGA Divisor Least Significant Byte Register. The BAL Register holds the least- significant byte of the BRGA divisor/count value. The Divisor Latch Access Bit (DLAB) bit in the LCR Register must be set to access this register (see Section 20.3.2.7).
Page 358: Brga Divisor Most Significant Byte Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.4 BRGA Divisor Most Significant Byte Register Register Bank: 0 BAH is the BRGA Divisor Most Significant Byte Register. The BAH Register holds the most-significant byte of the BRGA divisor/count value. The DLAB bit in the LCR Register must be set to access this register (see Section 20.3.2.7).
Page 359: General Enable Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.5 General Enable Register Register Bank: 0 GER is the General Enable Register. The GER Register enables or disables the bits of the GSR Register from being reflected in the GIR Register. GER acts as the Device Enable Register, masking the interrupt requests from the UART blocks.
Page 360: General Interrupt/Bank Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.6 General Interrupt/Bank Register Register Banks: 0, 1, 2, and 3 GIR is the General Interrupt/Bank Register. The GIR Register holds the highest priority enabled pending interrupt from the GSR Register. This register also holds a pointer to the current register segment.
Page 361: Table 20-17. Bank Select Bits [6:5]
UART2 LH75400/01/10/11 (Preliminary) User’s Guide Table 20-17. Bank Select Bits [6:5] BANK 1 BANK 0 SELECTED BANK 8250A/16450 Compatible Bank (Bank 0) General Work Bank (Bank 1) General Configuration Bank (Bank 2) Baud Rate Generation Configuration Bank (Bank 3) Table 20-18. Pending Interrupt Status Bits [3:1] PENDING INTERRUPT Not Used Transmit FIFO Interrupt (lowest priority)
Page 362: Line Control Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.7 Line Control Register Register Bank: 0 LCR is the Line Control Register. The LCR Register defines the basic configuration of the serial link. Table 20-19. LCR Register FIELD RESET FIELD PM2 PM1 RESET ADDR 0xFFFC2000 + 0x0C Table 20-20.
Page 363: Table 20-23. Character Bit Lengths
UART2 LH75400/01/10/11 (Preliminary) User’s Guide Table 20-21. Parity Modes PARITY SELECTED N Parity Odd Parity Even Parity High Parity Low Parity Software Parity Table 20-22. Stop Bit Lengths STOP BIT SBL2 SBL1 SBL0 LENGTH 6/4 or 8/4* NOTE: * 6/4 if character length is 6 bits; otherwise, 8/4. Table 20-23.
Page 364: Loopback Control Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.8 Loopback Control Register Register Banks: 0 and 1 MCTRL is the Loopback Control Register. The MCTRL Register places UART 2 into the Loopback Mode selected with the IMD Register (described in Section 20.3.2.23). For Bank 0, bit [4] is Read/Write and has a reset value of 0x00. For Bank 1, bit [4] is Read Only and its reset bits are indeterminate.
Page 365: Line Status Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.9 Line Status Register Register Bank: 0 LSR is the Line Status Register. The LSR Register holds the status of the serial link. It is provided for compatibility with the Intel 8250A UART. This register shares the following five bits with the RST Register (described in Section 20.3.2.17): •...
Page 366: Address/Control Character Register0
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.10 Address/Control Character Register0 Register Bank: 0 The ACTRL0 Register contains a byte that is compared to each received character. The exact function depends on the configuration of the IMD Register (see Section 20.3.2.23). In Normal Mode, this register can be used to program a special control character; in this case, a matched character is reported in the RST Register (see Section 20.3.2.17).
Page 367: Transmit Character Flag Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.11 Transmit Character Flag Register Register Banks: 1 TXF is the Transmit Flag Register The active bits used in this register are Write Only. The TXF Register holds additional components of the next character to be pushed into the Tx FIFO.
Page 368: Received Character Flags Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.12 Received Character Flags Register Register Bank: 1 RXF is the Received Character Flags Register. The RXF Register contains additional information about the character in the RXD Register. This register’s contents are loaded by the receiver simultaneously with the RXD Register. Table 20-33.
Page 369: Timer Control Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.13 Timer Control Register Register Bank: 1 TMCTRL is the Timer Control Register. The active bits used in this register are Write Only. The TMCTRL Register controls the operation of the following UART timers: • STA and TGA •...
Page 370: Timer Status Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.14 Timer Status Register Register Bank: 1 TMST is the Timer Status Register. The TMST Register holds the status of the timers. Bits [1] and [0] of this register generate interrupts that are reflected in the TIR bit (bit [5]) of the GSR Register (see Section 20.3.2.20).
Page 371: Fifo Level Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.15 FIFO Level Register Register Bank: 1 FLR is the FIFO Level Register. The FLR Register holds the current Receive and Transmit FIFO occupancy levels. Table 20-39. FLR Register FIELD RESET FIELD RFL2 RFL1 RFL0 TFL2 TFL1 TFL0 RESET ADDR...
Page 372: Receive Command Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.16 Receive Command Register Register Bank: 1 RCM is the Receive Command Register. The RCM Register controls the operation of the receive machine. The active bits used in this register are Write Only. Table 20-41. RCM Register FIELD RESET —...
Page 373: Receive Machine Status Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.17 Receive Machine Status Register Register Bank: 1 RST is the Receive Machine Status Register. The RST Register displays the status of the receive machine. It reports events that occurred since the RST was cleared. All RST Register contents, except bit [0], are cleared when it is read.
Page 374: Transmit Command Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.18 Transmit Command Register Register Bank: 1 TCM is the Transmit Command Register. The TCM Register enables or disables transmis- sion by the transmit machine, and clears the Tx FIFO. Table 20-45. TCM Register FIELD RESET —...
Page 375: Internal Command Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.19 Internal Command Register Register Bank: 1 ICM is the Internal Command Register. The active bits used in this register are Write Only. Table 20-47. ICM Register FIELD RESET — — — — — — —...
Page 376: General Status Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.20 General Status Register Register Bank: 1 GSR is the General Status Register. The GSR Register reflects all pending block-level interrupt requests. Each bit in the GSR Register reflects the status of a block and can be individually enabled by the GER Register (see Section 20.3.2.5).
Page 377: Fifo Mode Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.21 FIFO Mode Register Register Bank: 2 FMD is the FIFO Mode Register. The FMD Register configures the Tx and Rx FIFOs thresh- old levels; the number of characters contained in the FIFOs that can cause an interrupt. Table 20-51.
Page 378: Transmit Machine Mode Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.22 Transmit Machine Mode Register Register Bank: 2 TMD is the Transmit Machine Mode Register. The TMD Register, together with the LCR Register, defines the transmitter operating mode. Table 20-53. TMD Register FIELD RESET FIELD EED CED RESET ADDR...
Page 379: Internal Mode Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.23 Internal Mode Register Register Bank: 2 IMD is the Internal Mode Register. The IMD Register defines the General Device Operat- ing Mode. Table 20-55. IMD Register FIELD RESET µLM FIELD RESET ADDR 0xFFFC2000 + 0x10 Table 20-56.
Page 380: Address/Control Character Register 1
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.24 Address/Control Character Register 1 Register Bank: 2 Like the ACTRL0 Register, the ACTRL1 Register contains a byte that is compared to each received character. The value in ACTRL1 is usually a value different from the one in ACTRL0.
Page 381: Receive Interrupt Enable Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.25 Receive Interrupt Enable Register Register Bank: 2 RIE is the Receive Interrupt Enable Register. The RIE Register enables interrupts from the Rx state machine. It is used to mask out interrupt requests generated by the status bits of the RST Register (described in Section 20.3.2.17).
Page 382: Receive Machine Mode Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.26 Receive Machine Mode Register Register Bank: 2 RMD is the Receive Machine Mode Register. The RMD Register defines the receiver oper- ating mode. For information about manually locking the FIFO, see Section 20.3.2.16. Table 20-61. RMD Register FIELD RESET FIELD...
Page 383: Clocks Configure Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.27 Clocks Configure Register Register Bank: 3 CLCF is the Clocks Configure Register. The CLCF Register defines the transmit and receive code modes and sources. Table 20-63. CLCF Register FIELD RESET FIELD RESET ADDR 0xFFFC2000 + 0x00 Table 20-64.
Page 384: Brga Configuration Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.28 BRGA Configuration Register Register Bank: 3 BACF is the BRGA Configuration Register. The BACF Register defines the BRGA clock sources and operating mode. Table 20-65. BACF Register FIELD RESET FIELD RESET ADDR 0xFFFC2000 + 0x04 Table 20-66.
Page 385: Brgb Divisor Least Significant Byte Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.29 BRGB Divisor Least Significant Byte Register Register Bank: 3 BBL is the BRGB Divisor Least Significant Byte Register. The BBL Register contains the least-significant byte of the BRGB divisor/count value. Acceptable values for this register range from 2 to 65,535.
Page 386: Brgb Divisor Most Significant Byte Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.30 BRGB Divisor Most Significant Byte Register Register Bank: 3 BBH is the BRGB Divisor Most Significant Byte Register. The BBH Register contains the most-significant byte of the BRGB divisor/count value. The DLAB bit in the LCR Register must be set to access this register see Chapter 19, Section 19.3.1.9).
Page 387: Brgb Configuration Register
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.2.31 BRGB Configuration Register Register Bank: 3 BBCF is the BRGB Configuration Register. The BBCF Register defines the BRGB clock sources and operating mode. NOTE: BRGB can also obtain its input clock from the BRGA output. Table 20-71.
Page 388: Timer Interrupt Enable Register
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.2.32 Timer Interrupt Enable Register Register Bank: 3 TMIE is the Timer Interrupt Enable Register for the timer block. The TMIE Register masks- out interrupt requests generated by the status bits of the TMST Register. Table 20-73.
Page 389: Uart2 Interrupts
UART2 LH75400/01/10/11 (Preliminary) User’s Guide 20.3.3 UART2 Interrupts There are two levels of interrupt/status reporting within UART2: block-level interrupts and second-level interrupts. • Block-level interrupts include Rx FIFO, Tx FIFO, receiver, transmitter, and timer inter- rupts. The status of these blocks is reported in the General Status and General Interrupt Registers.
Page 390: Interrupt Service
LH75400/01/10/11 (Preliminary) User’s Guide UART2 20.3.3.2 Interrupt Service A service operation is an operation that the CPU performs that resets the particular status bit causing the UART2 interrupt. An interrupt request within UART 2 does not reset the sta- tus bit until the interrupt source is serviced. UART2 interrupt sources can be serviced in various ways.
Page 391: Figure 20-2. Interrupt And Status Reporting Structure
UART2 LH75400/01/10/11 (Preliminary) User’s Guide (HIGHEST PRIORITY) TIMER A EXPIRED TIMER TIMER B EXPIRED TX CONDITION TRANSMITTER ERROR RX PARITY ERROR OVERRUN ERROR BREAK DETECTED BREAK TERMINATED RX CONDITION INTERRUPT ADDRESS/CONTROL CHARACTER RECEIVED ADDRESS/CONTROL CHARACTER MATCH FRAMING ERROR RX FIFO LEVEL ABOVE RX FIFO THRESHOLD TX FIFO...
Page 392: Chapter 21 - General Purpose Input/Output
Chapter 21 General Purpose Input/Output The General Purpose Input/Output (GPIO) is a slave module that connects to the APB. The SoCs use five GPIO modules. Each module has two 8-bit ports, designated A through J, and provides 76 bits of programmable input/output. Figure 21-1 shows a block diagram of the GPIO.
Page 393: Gpio Features
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.1 GPIO Features The GPIO supports the following features. • 10 GPIO ports • Programmable port direction • All ports but one default to inputs at System Reset • Control word read-back capability. All GPIO pins are multiplexed with other functions.
Page 394: Gpio Programmer's Model
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.1 GPIO Programmer’s Model The base addresses for the GPIO modules are: Ports A and B: 0xFFFDF000 Ports C and D: 0xFFFDE000 Ports E and F: 0xFFFDD000 Ports G and H: 0xFFFDC000 Ports I and J: 0xFFFDB000 The location at offset 0x0C is reserved.
Page 395: Gpio Register Definitions
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3 GPIO Register Definitions 21.2.3.1 Port A Data Register PADR is the Port A Data Register. The active bits used in this register are Read/Write. Values written to PADR are output on the PA pins if the corresponding PADDR Data Direc- tion bits are set HIGH (port output).
Page 396: Port B Data Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.2 Port B Data Register PBDR is the Port B Data Register. The active bits used in this register are Read/Write. Values written to PBDR are output on the PB pins if the corresponding PBDDR Data Direc- tion bits are set HIGH (port output).
Page 397: Port A Data Direction Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.3 Port A Data Direction Register PADDR is the Port A Data Direction Register. The active bits used in this register are Read/Write. Bits set in PADDR Register set the corresponding PA pin to be an output. •...
Page 398: Port B Data Direction Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.4 Port B Data Direction Register PBDDR is the Port B Data Direction Register. The active bits used in this register are Read/Write. Bits set in the PBDDR Register set the corresponding PB pin to be an output: •...
Page 399: Port C Data Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.5 Port C Data Register PCDR is the Port C Data Register. The active bits used in this register are Read/Write. Values written to PCDR are output on the PC pins if the corresponding PCDDR Data Direc- tion bits are set HIGH (port output).
Page 400: Port D Data Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.6 Port D Data Register PDDR is the Port D Data Register. The active bits used in this register are Read/Write. Values written to PDDR are output on the PD pins if the corresponding PDDDR Data Direc- tion bits are set HIGH (port output).
Page 401: Port C Data Direction Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.7 Port C Data Direction Register PCDDR is the Port C Data Direction Register. The active bits used in this register are Read/Write. Bits set in the PCDDR Register set the corresponding PC pin to be an output: •...
Page 402: Port D Data Direction Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.8 Port D Data Direction Register PDDDR is the Port D Data Direction Register. The active bits used in this register are Read/Write. Bits set in the PDDDR set the corresponding PD pin to be an output: •...
Page 403: Port E Data Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.9 Port E Data Register PEDR is the Port E Data Register. The active bits used in this register are Read/Write. Values written to PEDR are output on the PE pins if the corresponding PEDDR Data Direc- tion bits are set HIGH (port output).
Page 404: Port F Data Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.10 Port F Data Register PFDR is the Port F Data Register. The active bits used in this register are Read/Write. Values written to PFDR will be output on the PF pins if the corresponding PFDDR Data Direction bits are set HIGH (port output).
Page 405: Port E Data Direction Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.11 Port E Data Direction Register PEDDR is the Port E Data Direction Register. The active bits used in this register are Read/Write. Bits set in PEDDR set the corresponding PE pin to be an output: •...
Page 406: Port F Data Direction Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.12 Port F Data Direction Register PFDDR is the Port F Data Direction Register. The active bits used in this register are Read/Write. Bits set in PFDDR set the corresponding PF pin to be an output: •...
Page 407: Port G Data Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.13 Port G Data Register PGDR is the Port G Data Register. The active bits used in this register are Read/Write. Values written to PGDR are output on the PG pins if the corresponding PGDDR Data Direction bits are set HIGH (port output).
Page 408: Port H Data Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.14 Port H Data Register PHDR is the Port H Data Register. The active bits used in this register are Read/Write. Values written to PHDR are output on the PH pins if the corresponding PHDDR Data Direc- tion bits are set HIGH (port output).
Page 409: Port G Data Direction Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.15 Port G Data Direction Register PGDDR is the Port G Data Direction Register. The active bits used in this register are Read/ Write. Bits set in PGDDR set the corresponding PG pin to be an output: •...
Page 410: Port H Data Direction Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.16 Port H Data Direction Register PHDDR is the Port H Data Direction Register. The active bits used in this register are Read/Write. Bits set in PHDDR set the corresponding PH pin to be an output: •...
Page 411: Port I Data Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.17 Port I Data Register PIDR is the Port I Data Register. The active bits used in this register are Read/Write. Values written to PIDR are output on the PI pins if the corresponding PIDDR Data Direction bits are set HIGH (port output).
Page 412: Port J Data Register
LH75400/01/10/11 (Preliminary) User’s Guide General Purpose Input/Output 21.2.3.18 Port J Data Register PJDR is the Port J Data Register. The active bits used in this register are Read/Write. A read from this register returns the current value on the corresponding port input. A System Reset clears all bits.
Page 413: Port I Data Direction Register
General Purpose Input/Output LH75400/01/10/11 (Preliminary) User’s Guide 21.2.3.19 Port I Data Direction Register PIDDR is the Port I Data Direction Register. Bits set in PIDDR set the corresponding PI pin to be an output: • Bit [7] controls pin 136 when the pin is configured as PI7. It does not control pin 136 when the pin is configured as LCDVD7.
Page 414: Chapter 22 - Controller Area Network
Chapter 22 Controller Area Network The Controller Area Network (CAN) block pertains to the LH75401 and LH75400 SoC devices only. The CAN 2.0B Controller is an AMBA-compliant peripheral that connects as a slave to the APB. The CAN Controller is located between the ARM processor and a CAN Transceiver, and is accessed through the AMBA port.
Page 415: Can 2.0B Features
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.1 CAN 2.0B Features The CAN Controller has the following features: • Full compliance with 2.0A and 2.0B Bosch specifications • Support for both 11-bit and 29-bit identifiers • Support for bit rates up to 1Mbit/s •...
Page 416: Protocols
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.2.1 Protocols The CAN specification consists of a basic protocol and a more advanced ‘full’ protocol: • The basic protocol involves a close association between the incoming data and the CPU. With this protocol, the CPU constantly checks incoming data. •...
Page 417: Remote Frame
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.2.2.2 Remote Frame The Remote frame is a request for information from a particular node. It is a message frame with the RTR bit set, followed by the control field that indicates the number of infor- mation bytes (0 to 8) it is requesting.
Page 418: Time Delays
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network Data received by the CAN Controller goes through an Acceptance Filter. The Acceptance Filter passes to the Receive FIFO only those messages that match the ones stored in the Acceptance Filter Registers. Acceptance filtering uses both the Acceptance Code Regis- ters ACCR0-3 and the Acceptance Mask Registers AMR0-3.
Page 419: Error Handling
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.2.7 Error Handling Errors are handled according to the CAN protocol. There are two types of errors that can occur: transmit errors and receive errors. The CAN Controller has two counters, one for transmission errors and one for reception errors.
Page 420: Can Register Summary
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.3.1 CAN Register Summary Table 22-1. CAN Register Summary TYPE ADDRESS RESET REGISTER DESCRIPTION NOTES OPERATING RESET OFFSET VALUE MODE MODE 0x00 Mode Register 0x01 0x04 Command Register 0x00 0x08 Status Register 0x3C 0x0C Interrupt Register 0x00...
Page 421: Can Register Definitions
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2 CAN Register Definitions 22.3.2.1 Mode Register MOD is the Mode Register. The active bits used in this register are Read/Write. The MOD Register allows the selection of: • Acceptance Filter Mode • Self Test Mode •...
Page 422: Command Register
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.3.2.2 Command Register CMR is the Command Register. The active bits used in this register are Write Only. Setting one or more of the usable bits starts an action in the CAN Controller’s transfer layer. Writ- ing a 0 to any bit has no effect.
Page 423: Status Register
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.3 Status Register SR is the Status Register. The SR Register reflects the status of the CAN Controller. It appears to the CPU as Read Only memory. If bits [5] and [4] are both 0, the CAN bus is idle. If both bits are 1, the Controller is waiting to become idle again.
Page 424: Table 22-7. Sr Register Definitions
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network Table 22-7. SR Register Definitions BITS NAME DESCRIPTION 31:8 Reserved Writing to these bits has no effect. Reading returns 0. Bus Status 0 = CAN Controller is involved in bus activities. 1 = CAN Controller is in the Bus Off state and not involved in bus activities. Error Status 0 = Both error counters are below the warning limit.
Page 425: Interrupt Register
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.4 Interrupt Register IR is the Interrupt Register. The IR Register allows the source of an interrupt to be identi- fied. When one or more bits of this register are set, the CAN Controller sends an interrupt to the CPU.
Page 426: Interrupt Enable Register
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.3.2.5 Interrupt Enable Register IER is the Interrupt Enable Register. This register selects the events that are indicated to the CPU through an interrupt being generated. It appears to the CPU as Read/Write memory. Table 22-10.
Page 427: Bus Timing Register 0
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.6 Bus Timing Register 0 BTR0 is one of two CAN Timing Registers (BTR1 is the other). Together, these two regis- ters define the structure of the bit period. The BTR0 Register defines the values of the Synchronization Jump Width (SJW) and the Bit Rate Prescaler (BRP).
Page 428: Bus Timing Register 1
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.3.2.7 Bus Timing Register 1 BTR1 is one of two CAN timing registers (BTR0 is the other). Together, these two registers define the structure of the bit period. The BTR1 Register defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point.
Page 429: Arbitration Lost Capture Register
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.8 Arbitration Lost Capture Register ALC is the Arbitration Lost Capture Register. This register records the bit position at which arbitration was lost. When bus arbitration is lost: • An Arbitration Lost Interrupt is generated (if enabled) and the current bit position of the Bit Processor is captured into this Arbitration Lost Capture Register.
Page 430: Table 22-18. Arbitration Losses
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network Table 22-18. Arbitration Losses DECIMAL ALC[4:0] DESCRIPTION NOTES VALUE 0 0 0 0 0 Arbitration lost in 1st bit of identifier (ID.28) 0 0 0 0 1 Arbitration lost in 2nd bit of identifier (ID.27) 0 0 0 1 0 Arbitration lost in 3rd bit of identifier (ID.26) 0 0 0 1 1...
Page 431: Error Code Capture Register
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.9 Error Code Capture Register ECC is the Error Code Capture Register. The ECC Register contains information about the type and location of errors on the bus. When a bus error occurs: • A Bus Error Interrupt is generated (if enabled) and the current bit position of the Bit Processor is captured into this Error Code Capture Register.
Page 432: Table 22-22. Segment Code
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network Table 22-22. Segment Code SEGMENT CODE BITS [4:0] DESCRIPTION 0 0 0 1 1 Start of frame 0 0 0 1 0 ID.28 to ID.21 0 0 1 1 0 ID.20 to ID.18 0 0 1 0 0 SRTR bit 0 0 1 0 1...
Page 433: Error Warning Limit Register
Controller Area Network LH75400/01/10/11 (Preliminary) User’s Guide 22.3.2.10 Error Warning Limit Register ELWR is the Error Warning Limit Register. The ELWR Register defines the number of errors after which an Error Warning Interrupt is generated, if enabled. The EWLR Register can only be written to in Reset Mode.
Page 434: Receive Error Counter Register
LH75400/01/10/11 (Preliminary) User’s Guide Controller Area Network 22.3.2.11 Receive Error Counter Register RXERR is the Receive Error Counter Register. The RXERR Register records the current value of the Receive Error Counter. After a System Reset or when a Bus Off event occurs, this register is au

Sharp Blue Treak LH75400 User Manual

Chapter 1 - Introduction

Chapter 12 - Direct Memory Access Controller

Chapter 13 - Color Liquid Crystal Display Controller

Chapter 14 - Liquid Crystal Display Controller

Chapter 16 - Watchdog Timer

Chapter 17 - Real-Time Clock

Chapter 18 - Synchronous Serial Port

Chapter 7 - Static Memory Controller

Chapter 2 - LH75401 Soc

Chapter 3 - LH75411 Soc

Chapter 4 - LH75400 Soc

Chapter 5 - LH75410 Soc

Chapter 6 - Memory Interface Architecture

Chapter 8 - Static Random Access Memory Controller

Chapter 9 - Reset, Clock, and Power Controller

Chapter 10 - Vectored Interrupt Controller

Chapter 11 - I/O Configuration

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