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Timers
15.2.2.14 Timer 2 Control Register (CTRL2)
This register allows programming various functions of the timer, including PWM Mode,
clock selection, and start/stop.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:15
14
13
12:11 CMP1
15-22
Table 15-30. CTRL2 Register
31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
///
PWM
TC
CMP1
0
0
0
0
0
RO
RW
RW
RW
RW
Table 15-31. CTRL2 Register Definitions
///
Reserved Reading this field returns 0. Write the reset value.
PWM Output This bit allows the use of CTCMP2A as a PWM output. This is
done by properly programming this bit as well as other bits in this register. Refer
to Section 15.1.3 for a complete explanation of this feature.
PWM
0 = Output CTCMP2A is normal and works only with the CMP2 Register.
1 = Output CTCMP2A is in PWM Mode.
Timer 2 Counter Operation This bit determines whether the counter is to oper-
ate as a free running counter or interval counter. When 1, the counter clears upon
matching CMP1 for Timer 2. This operation is only available with the CMP1 Reg-
TC
ister for Timer 2.
0 = Inhibit counter clear (operates as free running counter).
1 = Clear counter when CNT2 for Timer 2 matches CMP1 for Timer 2.
Output Value Select Timer/Counter Operation: Programs the value (when a
compare match occurs) output on the CTCMP2B pin when the CNT2 Register
matches T2CMP1.
00 = No change occurs to CTCMP2B
01 = Output 0 to CTCMP2B
10 = Output 1 to CTCMP2B
11 = Toggle the output to CTCMP2B
PWM Operation:
00 = Invalid
01 = Active HIGH PWM output polarity
10 = Active LOW PWM output polarity
11 = Invalid
IMPORTANT: CMP1 and CMP0 must be programmed to the same polarity.
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
CMP0
CAPB
0
0
0
0
RW
RW
RW
RW
0xFFFC4000 + 0x50
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
CAPA
SEL
0
0
0
0
0
RW
RW
RW
RW
RW
17
16
0
0
RO
RO
1
0
CS
CCL
0
0
RW
RW
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