Theory Of Operation - Sharp LH79524 User Manual

Chapter 18
Vectored Interrupt Controller
The LH79524 and LH97525 incorporate a Vectored Interrupt Controller (VIC). A vectored
interrupt has improved latency as it provides direct information about where service routines
are located and eliminates levels of software arbitration needed with a simpler interrupt con-
troller. Throughout this chapter all descriptions apply to both the LH79524 and LH97525.

18.1 Theory of Operation

The VIC provides hardware for initial prioritization and processing of up to 32 interrupts. Of
these 32 interrupts, 23 are routed from internal sources (such as the DMA controller, the
Watchdog Timer, etc.); 8 are from external interrupts; and 1 is a 'spare' and can be used
as a software interrupt-. Up to 16 interrupts can be assigned as vectored interrupts. The
VIC is programmed by application software, as are other functional blocks, via a set of reg-
isters. All 32 interrupt source lines can be enabled, disabled, and cleared individually, and
individual interrupt status may be determined.
All internal and external interrupts are routed to the VIC, where interrupt priority is deter-
mined by hardware. The CPU services the interrupt as either a vectored interrupt or a
default-vectored interrupt. A vectored interrupt results in a low-latency invocation of the
service routine for that particular interrupt. A default-vectored interrupt requires the CPU
to perform additional processing to determine which interrupt source caused the interrupt.
Any of the 32 lines can be assigned to any of the 16 interrupt vectors. Any line not explicitly
assigned to an interrupt vector is processed as a default-vectored interrupt. At reset, all
32 lines are set to be default-vectored interrupts.
Each interrupt line can be explicitly assigned as either an IRQ interrupt type (default)
or an FIQ interrupt type. Vectored-interrupt servicing is only available for IRQ interrupts.
Although more than one interrupt source can be designated as FIQ, only one source nor-
mally is designated to take advantage of the low latency of FIQ exception handling for a
specific need.
When an interrupt is being processed, other incoming, lower priority interrupt requests are
masked. Upon completion of in ISR, the mask is cleared, and the next lower priority inter-
rupt can be serviced.
On reset, the VIC is configured to pass all interrupts through to the CPU IRQ input as
default-vectored IRQ interrupts. In the reset configuration, the VIC Status Registers can
be used in a conventional way to service interrupts using the CPU IRQ Exception Vector
at address 0x18. Users must configure the VIC to use the vectored interrupt feature. Fol-
lowing reset, all interrupts are disabled.
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