Table 5-23. Curdhi Register; Table 5-24. Curdhi Fields; Table 5-25. Curdlo Register; Table 5-26. Curdlo Fields - Sharp LH79524 User Manual

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LH79524/LH79525 User's Guide

5.2.2.6 Current Destination Registers (CURDHI and CURDLO)

The Current Destination Registers are 16-bit Read Only registers that hold the current
value of the destination address pointer. The value in the registers is used as an AHB
address in a DMA-to-destination data transfer over the AHB. If the DeInc bit in the Control
Register is set to 1, the value in the Current Destination Registers increments as data
transfers from the DMA to a destination. The value increments at the end of the address
phase of the AHB transfer by the HSIZE value. If the DeInc bit is 0, the Current Destination
Register holds the same value during the entire DMA data transfer.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:0

Table 5-23. CURDHI Register

31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW
NAME
///
Reserved Reading returns 0. Write the reset value.
Current Destination Upper Address This field contains the upper 16-bits of
CURDHI
the address for the destination of data for the current DMA transfer.

Table 5-25. CURDLO Register

31
30
29
28
27
0
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
0
0
0
0
0
RW
RW
RW
RW
RW

Table 5-26. CURDLO Fields

NAME
///
Reserved Reading returns 0. Write the reset value.
Current Destination Lower Address This field contains the lower 16-bits
CURDLO
of the address for the destination of data for the current DMA transfer.
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
CURDHI
0
0
0
0
RW
RW
RW
RW
DATASTREAM x BASE + 0x020

Table 5-24. CURDHI Fields

DESCRIPTION
26
25
24
23
///
0
0
0
0
RO
RO
RO
RO
10
9
8
7
CURDLO
0
0
0
0
RW
RW
RW
RW
DATASTREAM x BASE + 0x024
DESCRIPTION
Version 1.0
Direct Memory Access Controller
22
21
20
19
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
0
0
0
0
RW
RW
RW
RW
RW
22
21
20
19
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
0
0
0
0
RW
RW
RW
RW
RW
18
17
16
0
0
0
RO
RO
2
1
0
0
0
0
RW
RW
18
17
16
0
0
0
RO
RO
2
1
0
0
0
0
RW
RW
5-13

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