Table 14-21. Dcr Register; Table 14-22. Dcr Fields; Dma Control Register (Dcr) - Sharp LH79524 User Manual

Synchronous Serial Port

14.2.2.10 DMA Control Register (DCR)

DCR is the DMA Control Register.
The RXDMAE and TXDMAE bits are not automatically cleared for standard Stream 0
through 3 DMA operations, respectively. These bits should be explicitly cleared by soft-
ware as soon as possible following DMA completion.
On initiating a DMA operation the DMAC:CTRL:ENABLE bit should be set before the RXD-
MAE bit, is set.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:2
1
0
14-20

Table 14-21. DCR Register

31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Transmit DMA Enable
TXDMAE
1 = DMA for the transmit FIFO is enabled
0 = Transmit DMA disabled
Receive DMA Enable
RXDMAE
1 = DMA for the receive FIFO is enabled
0 = Receive DMA disabled
26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
///
0 0 0 0
RO RO RO RO
0xFFFC6000 + 0x024

Table 14-22. DCR Fields

DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
0 0
RW RW