Figure 14-7. Microwire Frame Format (Continuous Transfers); Clock Generation - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide
SSPCLK
nSSPFRM
SSPTXD
SSPRXD

14.1.5 Clock Generation

The serial bit rate is derived by dividing down the SSP clock coming from the RCPC
that is a prescaled version of the system clock (see the RCPC chapter for detailed infor-
mation about setting up the system clock). The clock is first divided by an even prescale
value, DVSR, from 2 to 254, which is programmed in the CPSR Register. The clock is
further divided by a value from 1 to 256, which is CPD + 1 (where CPD is the value pro-
grammed in the CTRL0 Register). The frequency of the output clock SSPCLK is defined
as ƒ(SSPCLK) = (DVSR × (1 + CPD)).
14.1.6 Interrupts
The SSP can assert four types of interrupts. A single combined interrupt, comprising these
four signals, goes to the VIC:
• SSPRXINTR — SSP Receive FIFO Service Interrupt, locally maskable
• SSPTXINTR — SSP Transmit FIFO Service Interrupt, locally maskable
• SSPRORINTR — SSP Receive Overrun Interrupt, locally maskable
• SSPRXTOINTR — SSP Receive FIFO Timeout Interrupt
All four interrupts are combined into a single interrupt: SSPINTR. The status of the four
interrupt sources can be read from the MIS or RIS Register.
14.1.6.1 Receive Interrupt
SSPRXINTR is the Receive Interrupt. This interrupt is asserted when there are four or more
valid entries in the receive FIFO. The interrupt is cleared by reading the receive FIFO until
there are three or fewer entries.
LSB
0
MSB LSB
4 to 16 BITS
OUTPUT DATA

Figure 14-7. Microwire Frame Format (Continuous Transfers)

Version 1.0
MSB
8-BIT CONTROL
Synchronous Serial Port
LSB
MSB
LH79525-79
14-7