Instruction And Data Cache - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

1.7 Instruction and Data Cache

The ARM720T Core includes an 8KB Cache, Cache Controller, Memory-Management
Unit (MMU) and Write Buffer. A single cache is used for both instructions and data. The
cache is an important core feature because the AHB carries all Core, DMA, LCD Display,
and Ethernet traffic. For best bandwidth utilization, software should be structured to ensure
that the Core is running from within its cache whenever possible.
At reset, the Write Buffer, Cache, and MMU are disabled and the MMU's Translation
Lookaside Buffer (TLB) is flushed. If the MMU is utilized, software can determine memory
cachability by bank or by page. For best performance, the Color LCD frame buffer should
not be located in a cachable region.
1.8 Memory Management Unit (MMU)
The ARM720T core in the LH79524/LH79525 includes an MMU that performs three pri-
mary functions: It translates virtual addresses into physical addresses, it enables cache
and write buffering for particular ranges of virtual addresses, and it controls memory
access permissions. When the MMU is turned off, as it is at reset, all virtual addresses are
output directly onto the physical address bus (the AHB).
The MMU supports memory accesses based on 'sections' or 'pages' of memory. Sections
are 1MB blocks of memory; pages can be either small or large. Small pages consist of
4KB blocks of memory. Additional access control mechanisms are extended to 1KB
subpages. Large pages consist of 64KB blocks of memory. Large pages are supported
to allow mapping of a large region of memory while using only a single entry in the
Translation Lookaside Buffer (TLB). Additional access control mechanisms are extended
to 16KB subpages.
For more information about the core, cache, and MMU, refer to the ARM document
'ARM720T Processor Data Sheet', at www.arm.com.
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Overview
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